Method to form MOSFET with an elevated source/drain

Claim 1

A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an anti-reflection layer over said first silicon layer; forming a photoresist layer over said anti-reflection layer; defining a gate pattern on said photoresist layer; performing a reactive ion etching (RIE) using said gate pattern as a mask, to remove said portion of gate insulator layer, of said first silicon layer, and of said anti-reflection layer to define said gate region; removing said photoresist layer; doping said substrate with an energy between about 0.1 to 5 KeV to form an ultra-shallow extended source/drain junction in said substrate under a region uncovered by said gate region; forming an undoped spacer structure on sidewalls of said gate region; removing said anti-reflection layer; forming a second silicon layer on said semiconductor substrate and said first silicon layer; doping said second silicon layer to form a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; and performing a thermal process to said semiconductor substrate, in order to diffuse and active dopants in said extended source/drain junction and said source/drain junction.

Claim 2

A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an anti-reflection layer over said first silicon layer; forming a photoresist layer over said anti-reflection layer; defining a gate pattern on said photoresist layer; performing a reactive ion etching (RIE) using said gate pattern as a mask, to remove said portion of gate insulator layer, of said first silicon layer, and of said anti-reflection layer to define said gate region; removing said photoresist layer; doping said substrate with an energy between about 0.1 to 5 KeV to form an ultra-shallow extended source/drain junction in said substrate under a region uncovered by said gate region; forming an undoped spacer structure on sidewalls of said gate region; removing said anti-reflection layer; forming a second silicon layer on said semiconductor substrate and said first silicon layer; doping said second silicon layer to form a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; and performing a thermal process to said semiconductor substrate, in order to diffuse and active dopants in said extended source/drain junction and said source/drain junction.

Claim 13

A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an anti-reflection layer over said first silicon layer; forming a photoresist layer over said anti-reflection layer; defining a gate pattern on said photoresist layer; performing a reactive ion etching (RIE) using said gate pattern as a mask, to remove said portion of gate insulator layer, of said first silicon layer, and of said anti-reflection layer to define said gate region; removing said photoresist layer; doping said substrate with an energy between about 0.1 to 5 KeV to form an ultra-shallow extended source/drain junction in said substrate under a region uncovered by said gate region; thermally growing a dielectric layer on said substrate, sidewalls of said gate insulator layer and sidewalls of said first silicon layer; forming an undoped spacer structure of silicon oxide spacers on sidewalls of said gate region; removing said anti-reflection layer; forming a second silicon layer on said semiconductor substrate and said first silicon layer; doping said second silicon layer to form a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; and performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and said source/drain junction.

Claim 14

A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an anti-reflection layer over said first silicon layer; forming a photoresist layer over said anti-reflection layer; defining a gate pattern on said photoresist layer; performing a reactive ion etching (RIE) using said gate pattern as a mask, to remove said portion of gate insulator layer, of said first silicon layer, and of said anti-reflection layer to define said gate region; removing said photoresist layer; doping said substrate with an energy between about 0.1 to 5 KeV to form an ultra-shallow extended source/drain junction in said substrate under a region uncovered by said gate region; thermally growing a dielectric layer on said substrate, sidewalls of said gate insulator layer and sidewalls of said first silicon layer; forming an undoped spacer structure of silicon oxide spacers on sidewalls of said gate region; removing said anti-reflection layer; forming a second silicon layer on said semiconductor substrate and said first silicon layer; doping said second silicon layer to form a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; and performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and said source/drain junction.