Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure

Claim 1

A method for manufacturing a MOS transistor, comprising the sequential steps of: forming a gate oxide layer, a gate layer, and a first dielectric layer in sequence on a substrate on which isolation layers are already formed; etching said first dielectric layer and said gate layer in order to define a gate region; forming sidewall spacers on opposing sides of said gate region; forming a doped polysilicon layer overlying said isolation layers, said substrate, said sidewall spacers, and said gate region; etching the portion of said polysilicon layer overlying said isolation layers to achieve isolation between adjacent devices, and to form local interconnections; depositing a second dielectric layer; performing an annealing process to diffuse the dopant inside said polysilicon layer into said substrate, thereby forming a doped junction; performing a polishing process to remove the portion of said polysilicon layer overlying said gate region, thereby defining a completely isolated source region and drain region; depositing a third dielectric; and forming contact windows and metal layers contacting said gate, source, and drain regions.

Claim 2

A method for manufacturing a MOS transistor, comprising the sequential steps of: forming a gate oxide layer, a gate layer, and a first dielectric layer in sequence on a substrate on which isolation layers are already formed; etching said first dielectric layer and said gate layer in order to define a gate region; forming sidewall spacers on opposing sides of said gate region; forming a doped polysilicon layer overlying said isolation layers, said substrate, said sidewall spacers, and said gate region; etching the portion of said polysilicon layer overlying said isolation layers to achieve isolation between adjacent devices, and to form local interconnections; depositing a second dielectric layer; performing an annealing process to diffuse the dopant inside said polysilicon layer into said substrate, thereby forming a doped junction; performing a polishing process to remove the portion of said polysilicon layer overlying said gate region, thereby defining a completely isolated source region and drain region; depositing a third dielectric; and forming contact windows and metal layers contacting said gate, source, and drain regions.