US5268330A
Expired / Lapsed
US
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Process for improving sheet resistance of an integrated circuit device gate
Assignee: International Business Machines Corp
•
Filing: 1992-12-11
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Granted: 1993-12-07
•
Expires: 2012-12-11
Abstract
Abstract A passivating layer is deposited over an integrated circuit device, conventionally fabricated using silicidation, after which an insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of the passivating layer above the gate is removed with little or no effect on the insulating layer or gate. A trench above one or both junctions (source or drain) is formed by removing insulation using the passivating layer as an etch stop, then removing a portion of the passivating layer above the junction with little or no effect on the junction or any isolation region present. The gate may be further silicided, and the opening above the gate and the trench above the junction may each be planarly filled with a low sheet resistance conductive material, forming contacts. The contact above the junction may be borderless.
Inventors
- 👤 John H. Givens
- 👤 James S. Nakos
- 👤 Peter A. Burke
- 👤 Craig M. Hill
- 👤 Chung H. Lam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:48
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; Y; Y10; Y10S; Y10S438/00; Y10S438/934
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
195 words
A process for improving sheet resistance of an integrated circuit device gate during fabrication on a silicon substrate, said integrated circuit device including an integrated circuit structure comprising at least two junctions, a spacer between said gate and each said junction, and a thin dielectric layer between said gate and said substrate, said junctions having been previously silicided, said process comprising: depositing a passivating layer on said integrated circuit structure; depositing an insulating layer on said passivating layer; planarizing said insulating layer; planarly removing said planarized insulating layer to expose said passivating layer above said gate; removing said passivating layer above said gate selective to said insulating layer and said gate to expose a top of said gate; creating a trench in said insulating layer above at least one junction selective to said passivating layer; extending said trench through said passivating layer selective to said at least one junction; forming a first contact by planarly filling said exposed area above said gate with a first low sheet resistance conductive material; and forming a second contact by planarly filling said extending trench above said at least one junction with a second low sheet resistance conductive material.
Claim 2
Dependent Claim
195 words
A process for improving sheet resistance of an integrated circuit device gate during fabrication on a silicon substrate, said integrated circuit device including an integrated circuit structure comprising at least two junctions, a spacer between said gate and each said junction, and a thin dielectric layer between said gate and said substrate, said junctions having been previously silicided, said process comprising: depositing a passivating layer on said integrated circuit structure; depositing an insulating layer on said passivating layer; planarizing said insulating layer; planarly removing said planarized insulating layer to expose said passivating layer above said gate; removing said passivating layer above said gate selective to said insulating layer and said gate to expose a top of said gate; creating a trench in said insulating layer above at least one junction selective to said passivating layer; extending said trench through said passivating layer selective to said at least one junction; forming a first contact by planarly filling said exposed area above said gate with a first low sheet resistance conductive material; and forming a second contact by planarly filling said extending trench above said at least one junction with a second low sheet resistance conductive material.
Claim 3
Dependent Claim
18 words
The process of claim 1, wherein said first and second low sheet resistance conductive materials are the same.
Claim 4
Dependent Claim
14 words
The process of claim 2, wherein said low sheet resistance conductive material comprises tungsten.
Claim 5
Dependent Claim
70 words
The process of claim 2, wherein said exposed area above said gate and said extended trench are planarly filled by: depositing a layer of low sheet resistance conductive material over said insulating layer, said extended trench and said exposed area above said gate sufficient to fill said exposed area above said gate and said extended trench; and planarizing said low sheet resistance conductive material layer down to said insulating layer.
Claim 6
Dependent Claim
43 words
The process of claim 2, wherein said exposed area above said gate and said extended trench are planarly filled by selectively depositing low sheet resistance conductive material within said exposed area above said gate and said extended trench, such that planarization is unnecessary.
Claim 7
Dependent Claim
27 words
The process of claim 1, wherein said gate includes a silicon material, said process further comprising silicidation of said gate after exposing the top of said gate.
Claim 8
Dependent Claim
20 words
The process of claim 3, wherein said silicidation step includes reacting titanium with said gate to form a silicide material.
Claim 9
Dependent Claim
47 words
The process of claim 6, wherein silicidation of said gate is accomplished by: depositing a layer of reactive material over said insulating layer and said exposed area above said gate to react with said gate, forming a silicide; and removing any unreacted portion of said reactive material.
Claim 10
Dependent Claim
14 words
The process of claim 1, wherein said gate comprises p + doped polycrystalline silicon.
Claim 11
Dependent Claim
14 words
The process of claim 1, wherein said gate comprises n + doped polycrystalline silicon.
Claim 12
Dependent Claim
11 words
The process of claim 1, wherein said gate comprises polycrystalline silicon.
Claim 13
Dependent Claim
17 words
The process of claim 1, wherein said planarization of said insulating layer is accomplished by chemical-mechanical polishing.
Claim 14
Dependent Claim
18 words
The process of claim 1, wherein step of planarizing said insulating layer is accomplished by reactive ion etching.
Claim 15
Dependent Claim
16 words
The process of claim 1, wherein said gate includes a silicon material and is partially silicided.
Claim 16
Dependent Claim
12 words
The process of claim 1, wherein said passivating layer comprises silicon nitride.
Claim 17
Dependent Claim
18 words
The process of claim 1, wherein said passivating layer removal above said gate is accomplished by anisotropic etching.
Claim 18
Dependent Claim
13 words
The process of claim 16, wherein said anisotropic etching comprises reactive ion etching.
Claim 19
Dependent Claim
22 words
The process of claim 1, wherein said step of removing said passivating layer above said gate is further selective to said spacers.
Claim 20
Dependent Claim
223 words
A process for improving sheet resistance of an integrated circuit device gate during fabrication on a silicon substrate, said integrated circuit device including an integrated circuit structure comprising at least two junctions, a spacer between said gate and each of said junctions, an isolation region in said substrate next to at least one of said junctions, and a thin dielectric layer between said gate and said substrate, said junctions having been previously silicided, said process comprising: depositing a passivating layer on said integrated circuit structure; depositing an insulating layer on said passivating layer; planarizing said insulating layer; planarly removing said planarized insulating layer to exposed said passivating layer above said gate; removing said passivating layer above said gate selective to said insulating layer and said gate to expose a top of said gate; forming a trench in said insulating layer above said at least one junction selective to said passivating layer, said trench being partially above at least one junction and partially above said isolation region; extending said trench through said passivating layer selective to said at least one junction and said isolation region; forming a contact by planarly filling said exposed area above said gate with a first low sheet resistance conductive material; and forming a borderless contact by planarly filling said extended trench with a second low sheet resistance conductive material.
Claim 21
Dependent Claim
223 words
A process for improving sheet resistance of an integrated circuit device gate during fabrication on a silicon substrate, said integrated circuit device including an integrated circuit structure comprising at least two junctions, a spacer between said gate and each of said junctions, an isolation region in said substrate next to at least one of said junctions, and a thin dielectric layer between said gate and said substrate, said junctions having been previously silicided, said process comprising: depositing a passivating layer on said integrated circuit structure; depositing an insulating layer on said passivating layer; planarizing said insulating layer; planarly removing said planarized insulating layer to exposed said passivating layer above said gate; removing said passivating layer above said gate selective to said insulating layer and said gate to expose a top of said gate; forming a trench in said insulating layer above said at least one junction selective to said passivating layer, said trench being partially above at least one junction and partially above said isolation region; extending said trench through said passivating layer selective to said at least one junction and said isolation region; forming a contact by planarly filling said exposed area above said gate with a first low sheet resistance conductive material; and forming a borderless contact by planarly filling said extended trench with a second low sheet resistance conductive material.
Claim 22
Dependent Claim
18 words
The process of claim 19, wherein said first and second low sheet resistance conductive materials are the same.
Claim 23
Dependent Claim
14 words
The process of claim 20, wherein said low sheet resistance conductive material comprises tungsten.
Claim 24
Dependent Claim
70 words
The process of claim 20, wherein said exposed area above said gate and said extended trench are planarly filled by: depositing a layer of low sheet resistance conductive material over said insulating layer, said extended trench and said exposed area above said gate sufficient to fill said exposed area above said gate and said extended trench; and planarizing said low sheet resistance conductive material layer down to said insulating layer.
Claim 25
Dependent Claim
43 words
The process of claim 20, wherein said exposed area above said gate and said extended trench are planarly filled by selectively depositing low sheet resistance conductive material within said exposed area above said gate and said extended trench, such that planarization is unnecessary.
Claim 26
Dependent Claim
14 words
The process of claim 20, wherein said low sheet resistance conductive material comprises tungsten.
Claim 27
Dependent Claim
27 words
The process of claim 19, wherein said gate includes a silicon material, said process further comprising silicidation of said gate after exposing the top of said gate.
Claim 28
Dependent Claim
20 words
The process of claim 25, wherein said silicidation step includes reacting titanium with said gate to form a silicide material.
Claim 29
Dependent Claim
47 words
The process of claim 25, wherein silicidation of said gate is accomplished by: depositing a layer of reactive material over said insulating layer and said exposed area above said gate to react with said gate, forming a silicide; and removing any unreacting portion of said reactive material.
Claim 30
Dependent Claim
14 words
The process of claim 19, wherein said gate comprises p + doped polycrystalline silicon.
Claim 31
Dependent Claim
14 words
The process of claim 19, wherein said gate comprises n + doped polycrystalline silicon.
Claim 32
Dependent Claim
11 words
The process of claim 19, wherein said gate comprises polycrystalline silicon.
Claim 33
Dependent Claim
17 words
The process of claim 19, wherein said planarization of said insulating layer is accomplished by chemical-mechanical polishing.
Claim 34
Dependent Claim
19 words
The process of claim 19, wherein said step of planarizing said insulating layer is accomplished by reactive ion etching.
Claim 35
Dependent Claim
13 words
The process of claim 36, wherein said anisotropic etching comprises reactive ion etching.
Claim 36
Dependent Claim
16 words
The process of claim 19, wherein said gate includes a silicon material and is partially silicided.
Claim 37
Dependent Claim
12 words
The process of claim 19, wherein said passivating layer comprises silicon nitride.
Claim 38
Dependent Claim
18 words
The process of claim 19, wherein said passivating layer removal above said gate is accomplished by anisotropic etching.
Claim 39
Dependent Claim
22 words
The process of claim 19, wherein said step of removing said passivating layer above said gate is further selective to said spacers.
References Cited (Backward Citations)
US4518629A
Cited
US4587718A
Cited
US4740484A
Cited
US4690730A
Cited
US4746219A
Cited
US4877775A
Cited
US4849369A
Cited
US5013678A
Cited
US4753709A
Cited
US4795722A
Cited
US4824521A
Cited
US4994402A
Cited
US4755478A
Cited
US4966870A
Cited
JPH02283034A
Cited
US5081065A
Cited
US5022958A
Cited
US5034348A
Cited
US5086017A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |