Process for positioning an electrical contact hole between two interconnection lines of an integrated circuit

Claim 1

A process for positioning an electrical contact hole between a first interconnection line and a second interconnection line of an integrated circuit, comprising the steps of: forming the first interconnection line of the integrated circuit, and thereafter in successive stages: (a) depositing an insulating coating on the integrated circuit; (b) depositing on said insulating coating, a first coating of a material used for blanking or erasing a relief of the insulating coating and having a planar surface; (c) etching the first material coating, in order to bare the relief area of the insulating coating located above the first interconnection line; (d) defining the dimensions of the electrical contact hole to be formed by masking with the aid of a resin; (e) etching the insulating coating in order to form the electrical contact hole; (f) removing the mask and eliminating residual portions of the first material coating; (g) forming the second interconnection line in successive stages: (h) depositing a conductive coating in which the second interconnection line will be formed on the integrated circuit; (i) depositing on said conductive coating, a second coating of material for erasing or blanking the relief of the conductive coating and having a planar surface; (j) etching the second material coating in order to only leave material at the location of the electrical contact hole; (k) depositing a resin coating on the integrated circuit, so as to mask the second interconnection line to be formed; (l) etching the region of the conductive coating without resin or residual portions of the second material coating; and (m) eliminating the residual second material coating and the resin coating.