Method for forming a notched gate oxide asymmetric MOS device

Claim 1

A method of forming a MOS device in a semiconductor substrate, the method comprising: providing a hulk region having a first conductivity type in said semiconductor substrate; forming a notched gate dielectric and a gate electrode over a portion of said hulk region defining a channel region, wherein said forming said notched gate dielectric and said gate electrode further comprises: forming a first gate dielectric layer of a first thickness over said bulk region; forming a first polysilicon layer over said first gate dielectric layer; patterning said first gate dielectric layer and said first polysilicon layer such that they remain over only a first portion of said channel region; forming a second gate dielectric layer of a second thickness which is less than said first thickness, the second gate dielectric being located adjacent to said first gate dielectric layer remaining after said patterning, said second gate dielectric also being located over at least a second portion of said channel region, which second portion of said channel region is located outside of said first portion of said channel region; conformally forming a second polysilicon layer over at least said second gate dielectric and said first polysilicon layer; and anisotropically etching said second polysilicon layer such that said notched gate dielectric is formed having as its notch region said second gate dielectric layer overlying said second portion of said channel region; and forming source and drain regions of a second conductivity type separated by said channel region.

Claim 2

A method of forming a MOS device in a semiconductor substrate, the method comprising: providing a hulk region having a first conductivity type in said semiconductor substrate; forming a notched gate dielectric and a gate electrode over a portion of said hulk region defining a channel region, wherein said forming said notched gate dielectric and said gate electrode further comprises: forming a first gate dielectric layer of a first thickness over said bulk region; forming a first polysilicon layer over said first gate dielectric layer; patterning said first gate dielectric layer and said first polysilicon layer such that they remain over only a first portion of said channel region; forming a second gate dielectric layer of a second thickness which is less than said first thickness, the second gate dielectric being located adjacent to said first gate dielectric layer remaining after said patterning, said second gate dielectric also being located over at least a second portion of said channel region, which second portion of said channel region is located outside of said first portion of said channel region; conformally forming a second polysilicon layer over at least said second gate dielectric and said first polysilicon layer; and anisotropically etching said second polysilicon layer such that said notched gate dielectric is formed having as its notch region said second gate dielectric layer overlying said second portion of said channel region; and forming source and drain regions of a second conductivity type separated by said channel region.

Claim 4

A method of forming a MOS device in a semiconductor substrate, the method comprising: providing a bulk region having a first conductivity type in said semiconductor substrate; forming a notched gate dielectric and a gate electrode over a portion of said bulk region defining a channel region, said notched gate dielectric having a notch region of relatively thinner gate dielectric in comparison to said gate dielectric located outside of said notch region wherein, said forming of said notched gate dielectric and gate electrode is performed under conditions such that said gate electrode is laterally divided between a first gate region of a first conductivity type and a second gate region of a second conductivity type, and forming source and drain regions of said second conductivity type separated by said channel region.

Claim 5

A method of forming a MOS device in a semiconductor substrate, the method comprising: providing a bulk region having a first conductivity type in said semiconductor substrate; forming a notched gate dielectric and a gate electrode over a portion of said bulk region defining a channel region, said notched gate dielectric having a notch region of relatively thinner gate dielectric in comparison to said gate dielectric located outside of said notch region wherein, said forming of said notched gate dielectric and gate electrode is performed under conditions such that said gate electrode is laterally divided between a first gate region of a first conductivity type and a second gate region of a second conductivity type, and forming source and drain regions of said second conductivity type separated by said channel region.