Asymmetric low power MOS devices

Claim 1

An asymmetric MOS device on a semiconductor substrate, the MOS device comprising: a bulk region having an average dopant concentration of a first conductivity type; source and drain regions positioned within said bulk region and separated by a channel region, the source and drain regions having a dopant concentration of a second conductivity type; an asymmetric halo region having a dopant concentration of the first conductivity type, and abutting one of said source and drain regions and proximate said channel region effectively creating two pseudo-metal oxide semiconductor devices connected in series, a first pseudo device disposed away from the asymmetric halo region and having a first threshold voltage and a second pseudo device located proximate the asymmetric halo region and having a second threshold voltage which is higher in magnitude than the first threshold voltage, wherein the second pseudo device has a second effective channel length that is shorter than a first effective channel length of the first pseudo device and a substantial number of carriers can be transported across the channel of said second pseudo device ballistically; and a single gate electrode positioned over the channel region, wherein the wherein the device has a gate threshold voltage of at most about ±150 mV.