Process of fabricating floating gate type field effect transistor having drain region gently varied in impurity profile

Claim 1

A process of fabricating a floating gate type field effect transistor, comprising the steps of: a) preparing a semiconductor substrate of one conductivity type; b) forming a gate structure on a channel region in a major surface of said semiconductor substrate, said gate structure having a first gate insulating layer on said channel region, a floating gate electrode on said first gate insulating layer, a second gate insulating layer on said floating gate electrode and a control gate electrode on said second gate insulating layer; c) repeating an oblique ion-implantation with impurity atoms of the opposite conductivity type to said one conductivity type into a first area of said major surface on one side of said gate structure at different angles for forming a first drain sub-region varied in impurity concentration, a dose of said oblique ion-implantation being regulated to a middle value less than 1×10 15 cm -2 so as to hardly convert said first drain sub-region into an amorphous state and to produce hot carriers injected into said floating gate electrode; d) ion-implanting with impurity atoms of said opposite conductivity type into a part of said first area spaced from said gate structure for forming a second drain sub-region having an impurity concentration which is larger than the impurity concentration of said first drain sub-region, said first drain sub-region and said second drain sub-region being partially overlapped for forming a drain region; and e) completing said floating gate type field effect transistor.