Method of making very short channel length MNOS and MOS devices by double implantation of one conductivity type subsequent to other type implantation

Claim 1

A method for the manufacture of MNOS memory transistors with very short channel lengths utilizing a silicon substrate of a first conductivity type provided with a structured field oxide SiO 2 layer for the separation of the active transistor regions comprising the steps of: (a) forming a silicon oxide layer effective as a tunnel oxide on a surface of the silicon substrate of the first conductivity type; (b) applying a silicon nitride layer serving as a memory layer over the entire surface of the tunnel oxide layer; (c) structuring and retaining the memory nitride layer in the region of the memory transistor while selectively removing it elsewhere; (d) executing a surface-wide oxidation to form a gate oxide for the non-memory transistor and an oxynitride layer on the memory nitride; (e) precipitating a polysilicon layer and structuring the polysilicon layer as a gate electrode in the region of the memory transistor and of the non-memory transistor; (f) selectively applying a first layer of photosensitive resist to form an implantation mask over the field oxide regions and over the gate electrode of the memory transistor; (g) implanting ions of the first conductivity type into selected regions of the substrate; (h) stripping the photosensitive resist mask and diffusing ions of the first conductivity type into the substrate; (i) selectively applying a second layer of photosensitive resist to form an implantation mask in the region of the gate oxide for the non-memory transistor and of the gate oxide and oxynitride layer of the memory transistor; (j) implanting low energy ions of a second conductivity type forming source/drain zones; (k) stripping the photosensitive resist mask; (l) implanting higher energy ions of the second conductivity type thereby forming n+ regions active as source/drain zones and for generating the short channel; and (m) precipitating a protective intermediate oxide over the surface of the substrate, generating contact holes, and fabricating metal contacts.

Claim 2

A method for the manufacture of MNOS memory transistors with very short channel lengths utilizing a silicon substrate of a first conductivity type provided with a structured field oxide SiO 2 layer for the separation of the active transistor regions comprising the steps of: (a) forming a silicon oxide layer effective as a tunnel oxide on a surface of the silicon substrate of the first conductivity type; (b) applying a silicon nitride layer serving as a memory layer over the entire surface of the tunnel oxide layer; (c) structuring and retaining the memory nitride layer in the region of the memory transistor while selectively removing it elsewhere; (d) executing a surface-wide oxidation to form a gate oxide for the non-memory transistor and an oxynitride layer on the memory nitride; (e) precipitating a polysilicon layer and structuring the polysilicon layer as a gate electrode in the region of the memory transistor and of the non-memory transistor; (f) selectively applying a first layer of photosensitive resist to form an implantation mask over the field oxide regions and over the gate electrode of the memory transistor; (g) implanting ions of the first conductivity type into selected regions of the substrate; (h) stripping the photosensitive resist mask and diffusing ions of the first conductivity type into the substrate; (i) selectively applying a second layer of photosensitive resist to form an implantation mask in the region of the gate oxide for the non-memory transistor and of the gate oxide and oxynitride layer of the memory transistor; (j) implanting low energy ions of a second conductivity type forming source/drain zones; (k) stripping the photosensitive resist mask; (l) implanting higher energy ions of the second conductivity type thereby forming n+ regions active as source/drain zones and for generating the short channel; and (m) precipitating a protective intermediate oxide over the surface of the substrate, generating contact holes, and fabricating metal contacts.