Method of making a flash memory cell having an asymmetric source and drain pocket structure

Claim 1

A method of making a flash memory cell having an asymmetric source and drain pocket structure, comprising: successively forming a tunnel oxide layer, a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate of a first conductivity type; patterning the second conductive layer, the dielectric layer, the first conductive layer, and the tunnel oxide layer to form a gate electrode structure; performing a first ion implantation procedure to introduce a first impurity of a second conductivity type into the semiconductor substrate, thereby to form a heavily-doped source region and a heavily-doped drain region; performing a second ion implantation procedure at a tilt angle of 25° to 45°, to introduce a second impurity of the second conductivity type into the semiconductor substrate, so as to form a pair of asymmetric lightly-doped regions, with one of the asymmetric lightly-doped regions surrounding the heavily-doped source region, and the other of the asymmetric lightly-doped regions beneath the heavily-doped drain region; forming an insulating spacer on sidewalls of the gate electrode structure; coating a photoresist layer over exposed surfaces of the gate electrode structure, the insulating spacer, and the heavily-doped source and drain regions; patterning the photoresist layer to form an opening and expose a portion of the gate electrode structure, the insulating spacer, and the heavily-doped drain region; removing the exposed portion of the insulating spacer; performing a third ion implantation procedure at a tilt angle of 25° to 45°, to introduce an impurity of the first conductivity type into the semiconductor substrate, and forming a heavily-doped pocket region surrounding the heavily-doped drain region; and removing the photoresist layer.

Claim 2

A method of making a flash memory cell having an asymmetric source and drain pocket structure, comprising: successively forming a tunnel oxide layer, a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate of a first conductivity type; patterning the second conductive layer, the dielectric layer, the first conductive layer, and the tunnel oxide layer to form a gate electrode structure; performing a first ion implantation procedure to introduce a first impurity of a second conductivity type into the semiconductor substrate, thereby to form a heavily-doped source region and a heavily-doped drain region; performing a second ion implantation procedure at a tilt angle of 25° to 45°, to introduce a second impurity of the second conductivity type into the semiconductor substrate, so as to form a pair of asymmetric lightly-doped regions, with one of the asymmetric lightly-doped regions surrounding the heavily-doped source region, and the other of the asymmetric lightly-doped regions beneath the heavily-doped drain region; forming an insulating spacer on sidewalls of the gate electrode structure; coating a photoresist layer over exposed surfaces of the gate electrode structure, the insulating spacer, and the heavily-doped source and drain regions; patterning the photoresist layer to form an opening and expose a portion of the gate electrode structure, the insulating spacer, and the heavily-doped drain region; removing the exposed portion of the insulating spacer; performing a third ion implantation procedure at a tilt angle of 25° to 45°, to introduce an impurity of the first conductivity type into the semiconductor substrate, and forming a heavily-doped pocket region surrounding the heavily-doped drain region; and removing the photoresist layer.