Patent US6356486B1 successfully refreshed from Google Patents.
US6356486B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically alterable non-volatile memory with n-bits per cell
Assignee: MLC Intellectual Property LLC
•
Filing: 2000-06-05
•
Granted: 2002-03-12
•
Expires: 2020-06-05
Abstract
Abstract An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signals which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.
Inventors
- 👤 Gerald J. Banks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:42
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C16/14; G11C16/16; G11C16/32; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634; G11C2211/564; G11C2211/5642; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 180
Claim 1
Independent Claim
406 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile mutli-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the second reading reference parameter is allocated substantially at a midpoint between the second level and the third level, and the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 2
Dependent Claim
406 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile mutli-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the second reading reference parameter is allocated substantially at a midpoint between the second level and the third level, and the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 3
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 1 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 4
Dependent Claim
246 words
The electrically alterable non-volatile multi-level memory according to claim 2 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 5
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 3 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 6
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 4 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 7
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 5 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 8
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 6 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 9
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 7 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 10
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 1 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 11
Dependent Claim
404 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the second reading reference parameter is allocated substantially at a midpoint between the second level and the third level, and the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined parameter that is substantially different from the first predetermined value.
Claim 12
Dependent Claim
404 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the second reading reference parameter is allocated substantially at a midpoint between the second level and the third level, and the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined parameter that is substantially different from the first predetermined value.
Claim 13
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 10 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 14
Dependent Claim
245 words
The electrically alterable non-volatile multi-level memory according to claim 11 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the parameter of the non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 15
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 12 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 16
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 13 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 17
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 14 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 18
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 15 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 19
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 16 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 20
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 10 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 21
Dependent Claim
427 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the second reading reference parameter is allocated substantially at a midpoint between the second level and the third level, the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 22
Dependent Claim
427 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the second reading reference parameter is allocated substantially at a midpoint between the second level and the third level, the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 23
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 19 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 24
Dependent Claim
246 words
The electrically alterable non-volatile multi-level memory according to claim 20 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 25
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 21 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the parameter of the one nonv-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 26
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory accoridng to claim 22 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 27
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 23 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 28
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 24 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 29
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 25 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 30
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 19 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 31
Dependent Claim
421 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the second reading reference electrical value is allocated substantially at a midpoint between the second level and the third level, and the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 32
Dependent Claim
421 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the second reading reference electrical value is allocated substantially at a midpoint between the second level and the third level, and the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 33
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 28 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 34
Dependent Claim
273 words
The electrically alterable non-volatile multi-level memory according to claim 29 , wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrical value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 35
Dependent Claim
94 words
The electrically alterable non-volatile multi-level memory according to claim 30 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 36
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 31 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 37
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 32 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 38
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 33 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 39
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 34 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 40
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 28 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 41
Dependent Claim
412 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the second reading reference electrical value is allocated substantially at a midpoint between the second level and the third level, and the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 42
Dependent Claim
412 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the second reading reference electrical value is allocated substantially at a midpoint between the second level and the third level, and the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 43
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 37 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 44
Dependent Claim
273 words
The electrically alterable non-volatile multi-level memory according to claim 38 , wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrical value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 45
Dependent Claim
94 words
The electrically alterable non-volatile multi-level memory according to claim 39 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 46
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 40 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 47
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 41 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 48
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 42 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 49
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 43 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 50
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 37 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 51
Dependent Claim
445 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, and the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the second reading reference electrical value is allocated substantially at a midpoint between the second level and the third level, the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined vlaue that is substantially different from the first predetermined value.
Claim 52
Dependent Claim
445 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, and the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the second reading reference electrical value is allocated substantially at a midpoint between the second level and the third level, the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined vlaue that is substantially different from the first predetermined value.
Claim 53
Dependent Claim
32 words
The electrically alterable non-volatle multi-level memory according to claim 46 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 54
Dependent Claim
257 words
The electrically alterable non-volatile multi-level memory according to claim 47 , wherein the first reading reference electrical value, and the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrical value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 55
Dependent Claim
94 words
The electrically alterable non-volatile multi-level memory according to claim 48 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 56
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 49 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 57
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 50 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 58
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 51 , wherein said parameter of the first and second programming pulses is pulse width and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 59
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 52 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 60
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claims 46 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 61
Dependent Claim
386 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 62
Dependent Claim
386 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 63
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 55 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 64
Dependent Claim
246 words
The electrically alterable non-volatile multi-level memory according to claim 56 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 65
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 57 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 66
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 58 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 67
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 59 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 68
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 60 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 69
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 61 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 70
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 55 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 71
Dependent Claim
386 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 72
Dependent Claim
386 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 73
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 64 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 74
Dependent Claim
246 words
The electrically alterable non-volatile multi-level memory according to claim 65 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 75
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 66 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 76
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 67 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 77
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 68 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 78
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 69 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 79
Dependent Claim
59 words
The electrically non-volatile multi-level memory according to claim 70 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 80
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 64 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 81
Dependent Claim
410 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi- level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 82
Dependent Claim
410 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi- level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 83
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 73 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 84
Dependent Claim
246 words
The electrically alterable non-volatile multi-level memory according to claim 74 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 85
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 75 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parellel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 86
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 76 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 87
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 77 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 88
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 78 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 89
Dependent Claim
58 words
The electrically alterable non-volatile multi-level memory according to claim 79 , wherein each of the plurality of non-volatile multi-level cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of non-selected cell.
Claim 90
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 73 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 91
Dependent Claim
400 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 92
Dependent Claim
400 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 93
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 82 , wherein each of the multi-level memory cell includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 94
Dependent Claim
273 words
The electrically alterable non-volatile multi-level memory according to claim 83 , wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, including determing a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrical value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 95
Dependent Claim
94 words
The elecrically alterable non-volatile multi-level memory according to claim 84 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parellel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 96
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 85 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 97
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 86 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 98
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 87 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 99
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 88 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 100
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 82 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 101
Dependent Claim
400 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, and second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 102
Dependent Claim
400 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, and second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 103
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 91 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 104
Dependent Claim
273 words
The electrically alterable non-volatile multi-level memory according to claim 92 , wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrial value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 105
Dependent Claim
94 words
The electrically alterable non-volatile multi-level memory according to claim 93 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 106
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 94 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 107
Dependent Claim
34 words
The electrically alterable non-volatile multi-level memory according to claim 95 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 108
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 96 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 109
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 97 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 110
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 91 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 111
Dependent Claim
424 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 112
Dependent Claim
424 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate and a drain which is coupled to a bit line, electrons being capable of being injected into the floating gate, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to the bit line, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 113
Dependent Claim
31 words
The electrically alterable non-volatile multi-level memory according to claim 100 , wherein each of the multi-level memory includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 114
Dependent Claim
271 words
The electrically alterable non-volatile multi-level memory according to claim 101 , wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, includinig determining a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrical value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrival value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reference electrical value and the fourth verifying electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 115
Dependent Claim
94 words
The electrically alterable non-volatile multi-level memory according to claim 102 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between the bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 116
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 103 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 117
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 104 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 118
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 105 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 119
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 106 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 120
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 100 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 121
Dependent Claim
363 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 122
Dependent Claim
363 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 123
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 109 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 124
Dependent Claim
246 words
The electrically alterable non-volatile multi-level memory according to claim 110 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 125
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 111 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parellel between a bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 126
Dependent Claim
42 words
The electricaly alterable non-volatile multi-level memory according to claim 112 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 127
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 113 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 128
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 114 , wherein said paramter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 129
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 115 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 130
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 109 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 131
Dependent Claim
361 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of setting a parameter of at least one non-volatile memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 132
Dependent Claim
361 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of setting a parameter of at least one non-volatile memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 133
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 118 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 134
Dependent Claim
247 words
The electrically alterable non-volatile multi-level memory according to claim 119 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as out put data of a plurality of bits, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 135
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 120 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 136
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 121 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 137
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 122 , wherein the electrons are injfected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 138
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 123 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 139
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 124 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 140
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 118 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 141
Dependent Claim
385 words
An electrically alterable non-volatile multi-level memory including a pluraltiy of non-volatile multi-level memory cells, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 142
Dependent Claim
385 words
An electrically alterable non-volatile multi-level memory including a pluraltiy of non-volatile multi-level memory cells, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first level and the second level, the second reading reference parameter is allocated between the second level and the third level, and the third reading reference parameter is allocated between the third level and the fourth level, wherein the first reading reference parameter is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference parameter is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of setting the parameter of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 143
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 127 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 144
Dependent Claim
246 words
The electrically alterable non-volatile multi-level memory according to claim 128 , wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has attained the one level is conducted, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one level, and wherein the first verifying reference parameter is allocated at the first level and below the first reading reference parameter, the second verifying reference parameter is allocated at the second level and between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated at the third level and between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated at the fourth level and above the third reading reference parameter.
Claim 145
Dependent Claim
92 words
The electrically alterable non-volatile multi-level memory according to claim 129 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 146
Dependent Claim
42 words
The electrically alterable non-volatile multi-level memory according to claim 130 , wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 147
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 131 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 148
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 132 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 149
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 133 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 150
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 127 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 151
Dependent Claim
377 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 152
Dependent Claim
377 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 153
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 136 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 154
Dependent Claim
273 words
The electrically alterable non-volatile multi-level memory according to claim 137 , wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of he one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrical value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 155
Dependent Claim
94 words
The electrically alterable non-volatile multi-level memory according to claim 138 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 156
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 139 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 157
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 140 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 158
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 141 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 159
Dependent Claim
59 words
The electrically alterable non-volatile multi-level according to claim 142 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 160
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 136 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 161
Dependent Claim
376 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 162
Dependent Claim
376 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 163
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 145 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 164
Dependent Claim
273 words
The electrically alterable non-volatile multi-level memory according to claim 146 , wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrical value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 165
Dependent Claim
93 words
The electrically alterable non-volatile multi-level according to claim 147 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 166
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 148 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 167
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 149 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 168
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 150 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 169
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 151 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 170
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 145 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 171
Dependent Claim
401 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 172
Dependent Claim
401 words
An electrically alterable non-volatile multi-level memory including a plurality of non-volatile multi-level memory cells, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to attain one of a plurality of predetermined levels, including at least a first level representing a first memory state, a second level representing a second memory state, a third level representing a third memory state and a fourth level representing a fourth memory state, is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein thereafter an operation of reading status of the one non-volatile multi-level memory cell is carried out, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first level and the second level, the second reading reference electrical value is allocated between the second level and the third level, and the third reading reference electrical value is allocated between the third level and the fourth level, wherein the first reading reference electrical value is shifted toward the second level from a midpoint between the first level and the second level, and the third reading reference electrical value is shifted toward the third level from a midpoint between the third level and the fourth level, wherein the operation of controlling the electrical value of the one non-volatile multi-level memory cell includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell by applying a plurality of programming pulses to a control gate of the one non-volatile multi-level memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.
Claim 173
Dependent Claim
32 words
The electrically alterable non-volatile multi-level memory according to claim 154 , wherein each of the multi-level memory cells includes a floating gate FET having a channel with electrically alterable voltage threshold value.
Claim 174
Dependent Claim
273 words
The electrically alterable non-volatile multi-level memory according to claim 155 , wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has attained the one level is conducted, including determining a relationship between the electrical value of the one non-volatile multi-level memory cell and one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one level, and wherein the first verifying reference electrical value is allocated at the first level and below the first reading reference electrical value, the second verifying reference electrical value is allocated at the second level and between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated at the third level and between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated at the fourth level and above the third reading reference electrical value.
Claim 175
Dependent Claim
94 words
The electrically alterable non-volatile multi-level memory according to claim 156 , wherein channels of the floating gate FETs of the plurality of non-volatile multi-level memory cells are coupled in parallel between a bit line and a reference potential, and wherein the operation of reading status of the one non-volatile multi-level memory cell includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit.
Claim 176
Dependent Claim
43 words
The electrically alterable non-volatile multi-level memory according to claim 157 , wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.
Claim 177
Dependent Claim
36 words
The electrically alterable non-volatile multi-level memory according to claim 158 , wherein the electrons are injected into the floating gate of the one non-volatile multi-level memory cell by one of Fowler-Nordheim tunneling and hot electron injection.
Claim 178
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 159 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
Claim 179
Dependent Claim
60 words
The electrically alterable non-volatile multi-level memory according to claim 160 , wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and the control gate of a non-volatile multi-level memory cell selected to be programmed is supplied with a predetermined potential that is different from a potential supplied to the control gate of a non-selected cell.
Claim 180
Dependent Claim
45 words
The electrically alterable non-volatile multi-level memory according to claim 154 , wherein said parameter of the first and second programming pulses is pulse width, and the pulse width of the first programming pulse is substantially larger than the pulse width of the second programming pulse.
References Cited (Backward Citations)
US3660819A
Cited
US3755721A
Cited
US3801965A
Cited
US4054864A
Cited
US4004159A
Cited
US4122541A
Cited
US4139910A
Cited
US4090258A
Cited
US4149270A
Cited
US4181980A
Cited
USRE32401E
Cited
US4192014A
Cited
US4272830A
Cited
US4287570A
Cited
US4357685A
Cited
US4300210A
Cited
US4306300A
Cited
JPS56114199A
Cited
US4327424A
Cited
US4503518A
Cited
WO1982002276A1
Cited
US4415992A
Cited
US4449203A
Cited
US4612629A
Cited
US4417325A
Cited
US4448400A
Cited
US4388702A
Cited
US4462088A
Cited
US4495602A
Cited
US4627027A
Cited
US4586163A
Cited
US4558241A
Cited
US4709350A
Cited
US4578777A
Cited
US4653023A
Cited
US4661929A
Cited
US4771404A
Cited
US4799195A
Cited
JPS61239498A
Cited
JPS61239497A
Cited
US4733394A
Cited
JPS6224499A
Cited
US4701884A
Cited
US4853892A
Cited
US4847808A
Cited
US4809224A
Cited
US4903236A
Cited
US5014242A
Cited
JPH01159895A
Cited
US5021999A
Cited
US4964079A
Cited
FR2630574A1
Cited
US5268318A
Cited
US5168465A
Cited
US5642312A
Cited
US5712819A
Cited
US5043940A
Cited
US5095344A
Cited
US5568439A
Cited
US5583812A
Cited
US5554553A
Cited
US5198380A
Cited
US5544118A
Cited
US5434825A
Cited
US5293560A
Cited
US5268870A
Cited
US5268319A
Cited
US4989179A
Cited
US4890259A
Cited
US5262984A
Cited
US4914631A
Cited
EP0390404A2
Cited
US5172338A
Cited
US5163021A
Cited
US5172338B1
Cited
US5258958A
Cited
US5321655A
Cited
US5200959A
Cited
US5200920A
Cited
US5351210A
Cited
US5764571A
Cited
US6104640A
Cited
US5394362A
Cited
US5218569A
Cited
US5272669A
Cited
US5295255A
Cited
US5596527A
Cited
US5506813A
Cited
US5432735A
Cited
US5457650A
Cited
US5422845A
Cited
US5440505A
Cited
US5497119A
Cited
US5523972A
Cited
US5539690A
Cited
US5515317A
Cited
US5485422A
Cited
US5444656A
Cited
US5450363A
Cited
US5469384A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-11 | 2005-09-10 | 2006-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-11 | 2009-09-10 | 2010-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-11 | 2013-09-10 | 2014-03-12 | $7700.00 | Window Closed / Lapsed |