US4357685A
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Method of programming an electrically alterable nonvolatile memory
Assignee: STMicroelectronics SRL
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Filing: 1980-07-14
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Granted: 1982-11-02
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Expires: 2000-07-14
Abstract
Abstract A nonvolatile memory of the electrically alterable kind comprises an orthogonal array of cells each including a floating-gate IGFET and an enhancement IGFET in series. For the programming or the reading of a selected cell, lying at the intersection of a row and a column of the array, a common gate lead for all the enhancement IGFETs of the row and a common drain lead for all the enhancement IGFETs of the column are energized with voltage dependent on the desired kind of operation. To write a bit in a cell, its floating gate is progressively charged in a succession of steps separated by reading operations to check on the conduction threshold of the cell; the charging ends when that threshold reaches a predetermined storage level. To cancel a written bit, the floating gate is progressively discharged in a succession of steps again separated by reading operations; the discharging is terminated when the conduction threshold reaches a predetermined cancellation level. The width and/or the amplitude of a voltage pulse applied to an accessible gate of the floating-gate IGFET during the successive charging or discharging steps may be increased after each reading step in which the desired level is not attained.
Inventors
- 👤 Vincenzo Daniele
- 👤 Giuseppe Corda
- 👤 Aldo Magrucci
- 👤 Guido Torelli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:19
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/32; H10B; H10B69/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
185 words
A method of programming a nonvolatile electronic memory with a multiplicity of cells each producing, in response to a reading signal applied thereto, an output voltage depending upon the magnitude of a charge which is individually variable, by the application of charge-modifying potentials thereto, between a first absolute value not greater than a predetermined lower level and a second absolute value not less than a predetermined upper level, comprising the steps of: (a) applying to a selected cell, in the presence of a binary control voltage, a reading signal to determine whether a significant difference exists between said control voltage and said output voltage; (b) applying to the selected cell, upon detecting such a significant difference, a charge-modifying potential for a time sufficient to bring said output voltage closer to said control voltage; (c) repeating step (a), followed by step (b) if said difference persists, and continuing in like manner until said difference substantially disappears, the time of application of said charge-modifying potential being progressively lengthened with successive recurrences of step (b); and (d) generating a termination signal upon the substantial disappearance of said difference.
Claim 2
Independent Claim
185 words
A method of programming a nonvolatile electronic memory with a multiplicity of cells each producing, in response to a reading signal applied thereto, an output voltage depending upon the magnitude of a charge which is individually variable, by the application of charge-modifying potentials thereto, between a first absolute value not greater than a predetermined lower level and a second absolute value not less than a predetermined upper level, comprising the steps of: (a) applying to a selected cell, in the presence of a binary control voltage, a reading signal to determine whether a significant difference exists between said control voltage and said output voltage; (b) applying to the selected cell, upon detecting such a significant difference, a charge-modifying potential for a time sufficient to bring said output voltage closer to said control voltage; (c) repeating step (a), followed by step (b) if said difference persists, and continuing in like manner until said difference substantially disappears, the time of application of said charge-modifying potential being progressively lengthened with successive recurrences of step (b); and (d) generating a termination signal upon the substantial disappearance of said difference.
Claim 3
Independent Claim
183 words
A method of programming a nonvolatile electronic memory with a multiplicity of cells each producing, in response to a reading signal applied thereto, an output voltage depending upon the magnitude of a charge which is individually variable, by the application of charge-modifying potentials thereto, between a first absolute value not greater than a predetermined lower level and a second absolute value not less than a predetermined upper level, comprising the steps of: (a) applying to a selected cell, in the presence of a binary control voltage, a reading signal to determine whether a significant difference exists between said control voltage and said output voltage; (b) applying to a selected cell, upon detecting such a significant difference, a charge-modifying potential for a time sufficient to bring said output voltage closer to said control voltage; (c) repeating step (a), followed by step (b) if said difference persists, and continuing in like manner until said difference substantially disappears, the magnitude of said charge-modifying potential being progressively increased with successive recurrences of step (b); and (d) generating a termination signal upon the substantial disappearance of said difference.
Claim 4
Independent Claim
183 words
A method of programming a nonvolatile electronic memory with a multiplicity of cells each producing, in response to a reading signal applied thereto, an output voltage depending upon the magnitude of a charge which is individually variable, by the application of charge-modifying potentials thereto, between a first absolute value not greater than a predetermined lower level and a second absolute value not less than a predetermined upper level, comprising the steps of: (a) applying to a selected cell, in the presence of a binary control voltage, a reading signal to determine whether a significant difference exists between said control voltage and said output voltage; (b) applying to a selected cell, upon detecting such a significant difference, a charge-modifying potential for a time sufficient to bring said output voltage closer to said control voltage; (c) repeating step (a), followed by step (b) if said difference persists, and continuing in like manner until said difference substantially disappears, the magnitude of said charge-modifying potential being progressively increased with successive recurrences of step (b); and (d) generating a termination signal upon the substantial disappearance of said difference.
Claim 5
Dependent Claim
51 words
A method as defined in claim 1 or 2 wherein the time of application and the magnitude of said charge-modifying potential during the first occurrence of step (b) are chosen to be less than those required for a changeover of said output voltage between said first value and said second value.
Claim 6
Dependent Claim
77 words
A method as defined in claim 1 or 2 wherein said charge-modifying potentials, applied in step (b) to an electrode of the selected cell, are of relatively large absolute magnitude for a charge-increasing operation and of relatively small absolute magnitude for a charge-reducing operation, said reading signal including a reference pulse of intermediate absolute magnitude applied in step (a) to said electrode, said intermediate absolute magnitude being higher for a charge-increasing operation than for a charge-reducing operation.
Claim 7
Dependent Claim
59 words
A method as defined in claim 1 or 2 wherein each cell includes a floating-gate field effect transistor with an input electrode, an accessible writing gate and an accessible cancellation gate, said charge-modifying potential being applied to at least one of said accessible gates, said reading signal being applied to said input electrode and to both said accessible gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-01 | 1986-05-03 | 1986-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-01 | 1990-05-03 | 1990-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-01 | 1994-05-03 | 1994-11-02 | $7700.00 | Window Closed / Lapsed |