Variable threshold device memory circuit having automatic refresh feature

Claim 2

A temporary store memory circuit having a plurality of variable threshold level semiconductor memory cells, said circuit comprising: first means to apply a polarization voltage to selected semiconductor cells to vary the threshold level at times when the data stored and the data to be stored in such cells are different; second means to sense the threshold level of a selected semiconductor memory cell; and third means governed by the second means to apply the effective polarization voltage in accordance with a predetermined sensed threshold level at times when the threshold level is in a predetermined marginal state and the data stored and the data to be stored in such cells are the same.

Claim 3

A circuit according to claim 1 wherein the second means includes means to sense conductance that varies inversely as a function of the threshold level of the selected device; and the third means includes means to change the sensed conductance by a predetermined value, and includes means responsive to the sensed and predetermined conductance value to apply the polarizing voltage at times when the threshold level is below a predetermined level.

Claim 4

A temporary store memory circuit having a pair of variable threshold semiconductor devices for each memory cell, said circuit comprising: first means to apply a polarization voltage to each of the devices of a cell for operating the devices of a cell selectively to opposite low level and high level threshold states at times when the data stored and the data to be stored in the cells are different; second means governed by the relative threshold levels of the pair of devices to detect the data stored in the cell; third means governed by the second means to apply the effective polarization voltage in accordance with the relative threshold levels at times when the threshold levels are in a predetermined marginal state and the data stored and the data to be stored in such cell is the same.

Claim 5

A temporary store memory circuit having a pair of variable threshold semiconductor devices for each memory cell, said circuit comprising: first means to apply a polarization voltage to each of the devices of a cell for operating the devices of a cell selectively to opposite low level and high level threshold states at times when the data stored and the data to be stored in the cells are different; second means governed by the relative threshold levels of the pair of devices to detect the data stored in the cell; third means governed by the second means to apply the effective polarization voltage in accordance with the relative threshold levels at times when the threshold levels are in a predetermined marginal state and the data stored and the data to be stored in such cell is the same.

Claim 6

A memory circuit having a pair of variable threshold semiconductor devices for each memory cell, said circuit comprising: writing means for operating one device of each pair to a low threshold state and the other device of each pair to a high threshold state and vice versa to apply a polarizing voltage store selectively a binary one or a binary zero in each cell at times when the stored data is of the opposite state; each said device including an output for conducting a signal having a value representative of the threshold value of its associated device; detection means responsive to the relative values of the output signals of each pair of devices to generate a signal indicative of the binary data stored in each cell; inhibit means governed by the detection means signal to render the writing mean ineffective at times when the binary data to be written is the same as the binary data stored in each cell; and threshold level refreshing means governed by the binary data to be written to change by a predetermined amount the value of the output signal representative of the threshold value of at least one of the devices of each pair, said predetermined amount being selected such that the detection means generates a signal indicative of binary data opposite to that stored in each cell at times when the relative threshold levels of the devices are less than a predetermined value to apply the polarizing voltage at times when the threshold level is in a predetermined marginal state and the binary data to be written on the binary data stored is the same.

Claim 7

A memory circuit having a pair of variable threshold semiconductor devices for each memory cell, said circuit comprising: writing means for operating one device of each pair to a low threshold state and the other device of each pair to a high threshold state and vice versa to apply a polarizing voltage store selectively a binary one or a binary zero in each cell at times when the stored data is of the opposite state; each said device including an output for conducting a signal having a value representative of the threshold value of its associated device; detection means responsive to the relative values of the output signals of each pair of devices to generate a signal indicative of the binary data stored in each cell; inhibit means governed by the detection means signal to render the writing mean ineffective at times when the binary data to be written is the same as the binary data stored in each cell; and threshold level refreshing means governed by the binary data to be written to change by a predetermined amount the value of the output signal representative of the threshold value of at least one of the devices of each pair, said predetermined amount being selected such that the detection means generates a signal indicative of binary data opposite to that stored in each cell at times when the relative threshold levels of the devices are less than a predetermined value to apply the polarizing voltage at times when the threshold level is in a predetermined marginal state and the binary data to be written on the binary data stored is the same.

Claim 8

A circuit according to claim 4 wherein the output of each semiconductor device is a current value representative of the threshold level of its associated device; and the refreshing means includes means to add a selected current value to the device output representative of a high threshold level.