US4037243A
Expired / Lapsed
US
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Semi conductor memory cell utilizing sensing of variations in PN junction current conrolled by stored data
Assignee: Motorola Solutions Inc
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Filing: 1976-08-23
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Granted: 1977-07-19
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Expires: 1996-08-23
Abstract
Abstract Charge is stored on the gate of a gate controlled diode in a memory element to provide a junction breakdown memory cell. A quantity of charge representative of a logical 1 or a logical 0 may be dynamically stored in one embodiment. In another embodiment a composite silicon nitride/silicon dioxide dielectric is utilized to provide non-volatile storage of a logic state. Selection and sensing circuitry are coupled to an array of junction breakdown memory elements. Sensing circuitry detects the difference in reverse current of the gate controlled diode corresponding to a stored logical 1 and a stored logical 0, respectively.
Inventors
- 👤 Charles R. Hoffman
- 👤 Michael W. Powell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 00:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/39; H; H10; H10B; H10B69/00; H10D; H10D8/00; H10D8/812; H10D84/00; H10D84/201; H10D84/204
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
172 words
A junction memory cell comprising: a body of semiconductor of a first conductivity type having a surface; a first region of a second conductivity type in said body at said surface forming a PN junction with said body; dielectric means on said surface, said dielectric means including a first dielectric layer of a first dielectric material on said surface covering a junction between said body and said first region, said dielectric means also including a second dielectric layer of a second type dielectric material on said first dielectric layer; gate electrode means located on said second dielectric layer for controlling a reverse junction current generated by said PN junction responsive to charge representative of a logical "1" or a logical "0" stored in said dielectric means; data input means coupled to said gate electrode means for effecting writing said logical "1" or said logical "0" into said dielectric means; and sensing output means coupled to said second region for effecting sensing said reverse junction current during reading of said junction memory cell.
Claim 2
Dependent Claim
172 words
A junction memory cell comprising: a body of semiconductor of a first conductivity type having a surface; a first region of a second conductivity type in said body at said surface forming a PN junction with said body; dielectric means on said surface, said dielectric means including a first dielectric layer of a first dielectric material on said surface covering a junction between said body and said first region, said dielectric means also including a second dielectric layer of a second type dielectric material on said first dielectric layer; gate electrode means located on said second dielectric layer for controlling a reverse junction current generated by said PN junction responsive to charge representative of a logical "1" or a logical "0" stored in said dielectric means; data input means coupled to said gate electrode means for effecting writing said logical "1" or said logical "0" into said dielectric means; and sensing output means coupled to said second region for effecting sensing said reverse junction current during reading of said junction memory cell.
Claim 3
Dependent Claim
25 words
A junction memory cell as recited in claim 1 wherein said first dielectric layer is silicon dioxide and said second dielectric layer is silicon nitride.
Claim 4
Dependent Claim
76 words
A junction memory cell as recited in claim 1 further including a second region of said second conductivity type spaced from said first region, said first dielectric layer covering a junction between said body and said second region, said second dielectric layer being substantially thicker over said junction between said body and said second region and over said space between said first and second regions and over said junction between said first region and said body.
Claim 5
Dependent Claim
22 words
The junction memory cell as recited in claim 3 wherein said gate conductor extends over said space on said first dielectric layer.
Claim 6
Dependent Claim
23 words
The junction memory cell as recited in claim 1 further including a coupling MOSFET coupled between said first region and a sense conductor.
Claim 7
Dependent Claim
22 words
The junction memory cell as recited in claim 5 wherein a gate of said coupling MOSFET is coupled to said gate conductor.
Claim 8
Dependent Claim
202 words
A read/write memory storage cell located in a first region of first conductivity type semiconductor comprising: a second region of second conductivity type semiconductor located in said first region at a surface thereof; a third region of said first conductivity type semiconductor located in said second region at said surface, said second and third regions forming a PN junction at said surface, wherein said PN junction generates a reverse junction current representative of a logical "1" or a logical "0" stored in said read/write memory storage cell when said PN junction is reverse biased; a data means for conducting a voltage representative of a logical "1" or a logical "0" to be written into said read/write memory storage cell; a sense means coupled to said third region for conducting said reverse junction current during reading of said read/write memory storage cell; gate insulator means on said surface covering a portion of said PN junction; and gate electrode means located on said gate insulator means and coupled to said data means for controlling said reverse junction current responsive to charge representative of said logical "1" or said logical "0" written into said read/write memory storage cell and stored on said gate electrode means.
Claim 9
Dependent Claim
202 words
A read/write memory storage cell located in a first region of first conductivity type semiconductor comprising: a second region of second conductivity type semiconductor located in said first region at a surface thereof; a third region of said first conductivity type semiconductor located in said second region at said surface, said second and third regions forming a PN junction at said surface, wherein said PN junction generates a reverse junction current representative of a logical "1" or a logical "0" stored in said read/write memory storage cell when said PN junction is reverse biased; a data means for conducting a voltage representative of a logical "1" or a logical "0" to be written into said read/write memory storage cell; a sense means coupled to said third region for conducting said reverse junction current during reading of said read/write memory storage cell; gate insulator means on said surface covering a portion of said PN junction; and gate electrode means located on said gate insulator means and coupled to said data means for controlling said reverse junction current responsive to charge representative of said logical "1" or said logical "0" written into said read/write memory storage cell and stored on said gate electrode means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-18 | 1981-01-17 | 1981-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-18 | 1985-01-17 | 1985-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-18 | 1989-01-17 | 1989-07-19 | $7700.00 | Window Closed / Lapsed |