Nonvolatile memory cell

Claim 2

An integrated circuit array of nonvolatile memory cells comprising: a. a silicon wafer of a first conductivity type; b. columns of MNOS memory transistors, each having a permanently ionizable insulator layer therein, built into said silicon wafer; c. columns of fixed threshold control transistors also built into said silicon wafer, with a column of said fixed threshold control transistors being associated with each of said columns of MNOS memory transistors, said columns of said fixed threshold control transistors being disposed in said silicon wafer alternately with respect to said columns of MNOS memory transistors, the drain electrode of each fixed threshold control transistor in one column being electrically connected to the gate electrode of an MNOS memory transistor in an adjacent column, to control the application of a set potential to any one of the MNOS memory transistors in said adjacent column of MNOS memory transistors; and d. an isolation region of opposite conductivity to said first conductivity in said silicon wafer between said columns of MNOS memory transistors and said columns of fixed threshold control transistors.

Claim 3

An integrated circuit array of nonvolatile memory cells having means for setting or resetting a selected memory cell of said integrated circuit array without affecting the other nonvolatile memory cells in said integrated circuit array, comprising: a. a silicon wafer of a first conductivity type; b. columns of MNOS memory transistors, each having a permanently ionizable insulator layer therein, built into said silicon wafer; c. columns of fixed threshold control transistors also built into said silicon wafer, with a column of said fixed threshold control transistors being associated with each of said columns of MNOS memory transistors, said columns of said fixed threshold control transistors being disposed in said silicon wafer alternately with respect to said columns of MNOS memory transistors, the drain electrode of each fixed threshold control transistor in one column being electrically connected to the gate electrode of an MNOS memory transistor in an adjacent column, to control the application of a set potential or a reset potential to any one of the MNOS memory transistors in said adjacent column of MNOS memory transistors; and d. an isolation region of opposite conductivity to said first conductivity isolation in said silicon wafer between said columns of MNOS memory transistors and said columns of fixed threshold control transistors; e. first electrical means connected to gate electrodes of rows of said fixed threshold control transistors for conducting a set potential therethrough to the gate electrodes of a selected row of MNOS memory transistors; f. second electrical means connected to the source electrodes of said columns of said fixed threshold control transistors for applying a set potential through conductive fixed threshold control transistors to the gatE electrodes of their MNOS memory transistors, to permanently set these MNOS memory transistors by ionizing the insulator layers of these MNOS memory transistors; g. third electrical means connected to said rows of the gate electrodes of said fixed threshold control transistors for conducting a reset potential therethrough; and h. fourth electrical means connected to the source electrodes of said columns of said fixed threshold control transistors for applying a reset potential through conductive fixed threshold control transistors to the gate electrodes of their associated MNOS memory transistors, to permanently reset these MNOS memory transistors by deionizing the insulator layers of these MNOS memory transistors.

Claim 4

An integrated circuit array of nonvolatile memory cells having means for setting or resetting a selected memory cell of said integrated circuit array without affecting the other nonvolatile memory cells in said integrated circuit array, comprising: a. a silicon wafer of a first conductivity type; b. columns of MNOS memory transistors, each having a permanently ionizable insulator layer therein, built into said silicon wafer; c. columns of fixed threshold control transistors also built into said silicon wafer, with a column of said fixed threshold control transistors being associated with each of said columns of MNOS memory transistors, said columns of said fixed threshold control transistors being disposed in said silicon wafer alternately with respect to said columns of MNOS memory transistors, the drain electrode of each fixed threshold control transistor in one column being electrically connected to the gate electrode of an MNOS memory transistor in an adjacent column, to control the application of a set potential or a reset potential to any one of the MNOS memory transistors in said adjacent column of MNOS memory transistors; and d. an isolation region of opposite conductivity to said first conductivity isolation in said silicon wafer between said columns of MNOS memory transistors and said columns of fixed threshold control transistors; e. first electrical means connected to gate electrodes of rows of said fixed threshold control transistors for conducting a set potential therethrough to the gate electrodes of a selected row of MNOS memory transistors; f. second electrical means connected to the source electrodes of said columns of said fixed threshold control transistors for applying a set potential through conductive fixed threshold control transistors to the gatE electrodes of their MNOS memory transistors, to permanently set these MNOS memory transistors by ionizing the insulator layers of these MNOS memory transistors; g. third electrical means connected to said rows of the gate electrodes of said fixed threshold control transistors for conducting a reset potential therethrough; and h. fourth electrical means connected to the source electrodes of said columns of said fixed threshold control transistors for applying a reset potential through conductive fixed threshold control transistors to the gate electrodes of their associated MNOS memory transistors, to permanently reset these MNOS memory transistors by deionizing the insulator layers of these MNOS memory transistors.

Claim 5

An integrated circuit array of nonvolatile memory cells for setting or resetting any one nonvolatile memory cell of said integrated circuit array without affecting any other nonvolatile memory cell of said integrated circuit array, comprising: a. a silicon wafer of a first conductivity type; b. spaced columns of MNOS memory transistors, each having a permanently ionizable insulator layer therein, built into said silicon wafer; c. columns of fixed threshold control transistors interdigitated with said spaced columns of MNOS memory transistors also built into said silicon wafers, with a column of said fixed threshold control transistors being associated with each of said columns of MNOS memory transistors, said columns of said fixed threshold control transistors being disposed in said silicon wafer alternately with respect to said columns of MNOS memory transistors, the drain electrode of each fixed threshold control transistor in one column being electrically connected to the gate electrode of an MNOS memory transistor in an adjacent column, to control the application of a set potential or a reset potential to selected MNOS memory transistors in said adjacent column of MNOS memory transistors; and d. an isolation region of opposite conductivity to said first conductivity in said silicon wafer between said columns of MNOS memory transistors and said columns of fixed threshold control transistors; e. write-x-select means connected to the gate electrodes of rows of said fixed threshold control transistors for conducting a set potential or a reset potential therethrough to the gate electrodes of a selected row of MNOS memory transistors; and f. write-y-select means connected to the source electrodes of said columns of said fixed threshold control transistors for applying a set potential through said conductive fixed threshold control transistors to the gate electrodes of their associated MNOS memory transistors to place said associated MNOS memory transistors in a set state, or for simultaneously applying a reset potential through said conductive fixed threshold control transistors to the gate electrodes of their associated memory transistors, to place said MNOS memory transistors in a reset state.

Claim 6

An integrated circuit array of nonvolatile memory cells for setting or resetting any one nonvolatile memory cell of said integrated circuit array without affecting any other nonvolatile memory cell of said integrated circuit array, comprising: a. a silicon wafer of a first conductivity type; b. spaced columns of MNOS memory transistors, each having a permanently ionizable insulator layer therein, built into said silicon wafer; c. columns of fixed threshold control transistors interdigitated with said spaced columns of MNOS memory transistors also built into said silicon wafers, with a column of said fixed threshold control transistors being associated with each of said columns of MNOS memory transistors, said columns of said fixed threshold control transistors being disposed in said silicon wafer alternately with respect to said columns of MNOS memory transistors, the drain electrode of each fixed threshold control transistor in one column being electrically connected to the gate electrode of an MNOS memory transistor in an adjacent column, to control the application of a set potential or a reset potential to selected MNOS memory transistors in said adjacent column of MNOS memory transistors; and d. an isolation region of opposite conductivity to said first conductivity in said silicon wafer between said columns of MNOS memory transistors and said columns of fixed threshold control transistors; e. write-x-select means connected to the gate electrodes of rows of said fixed threshold control transistors for conducting a set potential or a reset potential therethrough to the gate electrodes of a selected row of MNOS memory transistors; and f. write-y-select means connected to the source electrodes of said columns of said fixed threshold control transistors for applying a set potential through said conductive fixed threshold control transistors to the gate electrodes of their associated MNOS memory transistors to place said associated MNOS memory transistors in a set state, or for simultaneously applying a reset potential through said conductive fixed threshold control transistors to the gate electrodes of their associated memory transistors, to place said MNOS memory transistors in a reset state.

Claim 7

An integrated circuit array of nonvolatile memory cells for setting or resetting a selected nonvolatile memory cell within said integrated circuit array and for also reading the state of a selected nonvolatile memory cell within said integrated circuit array, comprising: a. a silicon wafer of a first conductivity type; b. spaced columns of MNOS memory transistors, each having a permanently ionizable insulator layer therein, built into said silicon wafer; c. columns of fixed threshold control transistors also built into said silicon wafer, with a column of said fixed threshold control transistors being associated with each of said columns of MNOS memory transistors, said columns of said fixed threshold control transistors being disposed in said silicon wafer alternately with respect to said columns of MNOS memory transistors, the drain electrode of each fixed threshold control transistor in one column being electrically connected with the gate eleCtrode of an MNOS memory transistor in an adjacent column, to control the application of a set potential or a reset potential to any one of the MNOS memory transistors in said adjacent column of MNOS memory transistors; and d. an isolation region of opposite conductivity to said first conductivity in said silicon wafer between said columns of MNOS memory transistors and said columns of fixed threshold control transistors; e. write-x-select means connected to the gate electrodes of rows of said fixed threshold control transistors for conducting a set potential or a reset potential therethrough to the gate electrode of a selected MNOS memory transistor; f. write-y-select means connected to the source electrodes of said columns of said fixed threshold control transistors for applying a set potential through said conductive fixed threshold control transistors to the gate electrodes of their associated MNOS memory transistors to place said associated MNOS memory transistor in a set state, or for applying a reset potential through said conductive fixed threshold control transistors to the gate electrodes of their associated MNOS memory transistors, to place said MNOS memory transistors in a reset state; g. read-y-select means connected to columns of the source electrodes of said MNOS memory transistors for passing a current through any set MNOS transistor of a column of MNOS memory transistors; and h. sense-out means connected to rows of the drain electrodes of said MNOS memory transistors for sensing for the passage of current through the MNOS memory transistors in any column of MNOS memory transistors to determine which MNOS memory transistors in said column are set and which are reset.

Claim 8

An integrated circuit array of nonvolatile memory cells for setting or resetting a selected nonvolatile memory cell within said integrated circuit array and for also reading the state of a selected nonvolatile memory cell within said integrated circuit array, comprising: a. a silicon wafer of a first conductivity type; b. spaced columns of MNOS memory transistors, each having a permanently ionizable insulator layer therein, built into said silicon wafer; c. columns of fixed threshold control transistors also built into said silicon wafer, with a column of said fixed threshold control transistors being associated with each of said columns of MNOS memory transistors, said columns of said fixed threshold control transistors being disposed in said silicon wafer alternately with respect to said columns of MNOS memory transistors, the drain electrode of each fixed threshold control transistor in one column being electrically connected with the gate eleCtrode of an MNOS memory transistor in an adjacent column, to control the application of a set potential or a reset potential to any one of the MNOS memory transistors in said adjacent column of MNOS memory transistors; and d. an isolation region of opposite conductivity to said first conductivity in said silicon wafer between said columns of MNOS memory transistors and said columns of fixed threshold control transistors; e. write-x-select means connected to the gate electrodes of rows of said fixed threshold control transistors for conducting a set potential or a reset potential therethrough to the gate electrode of a selected MNOS memory transistor; f. write-y-select means connected to the source electrodes of said columns of said fixed threshold control transistors for applying a set potential through said conductive fixed threshold control transistors to the gate electrodes of their associated MNOS memory transistors to place said associated MNOS memory transistor in a set state, or for applying a reset potential through said conductive fixed threshold control transistors to the gate electrodes of their associated MNOS memory transistors, to place said MNOS memory transistors in a reset state; g. read-y-select means connected to columns of the source electrodes of said MNOS memory transistors for passing a current through any set MNOS transistor of a column of MNOS memory transistors; and h. sense-out means connected to rows of the drain electrodes of said MNOS memory transistors for sensing for the passage of current through the MNOS memory transistors in any column of MNOS memory transistors to determine which MNOS memory transistors in said column are set and which are reset.