US3846766A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Associative memories including mos transistors
Assignee: Toshiba Corp
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Filing: 1973-08-30
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Granted: 1974-11-05
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Expires: 1993-08-30
Abstract
Abstract An associative memory comprises at least one memory cell constituted by two MIOS transistors having hysteresis gate threshold voltage characteristics. The MIOS transistors are combined such that for a gate voltage of a selected value, one MIOS transistor is in ON state whereas the other OFF state. These states correspond to a binary ''''1.'''' On the other hand, the states where said one MIOS transistor is in OFF state and the other ON state correspond to binary ''''0.
Inventors
- 👤 I Nojima
- 👤 K Tamaru
- 👤 T Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:04
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C15/00; G11C15/04; G11C15/046; H; H10; H10B; H10B99/00; H10B99/22
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
224 words
An associative memory comprising one bit memory cell including: a pair of MIOS transistors each having a source electrode, a drain electrode, and a gate electrode including double insulating layers and presenting threshold voltage-hysteresis characteristics; a word line connected commonly to the gate electrodes of said pair of MIOS transistors; a pair of digit lines connected respectively to the drain electrodes of said pair of MIOS transistors; a read-out line connected commonly to the source electrodes of said pair of MIOS transisotrs; writing means for writing a binary signal, including means for selectively impressing voltages of different levels respectively on said pair of digit lines according to the content of said binary signal and for selectively impressing at the same time on said word line a negative or positive polarity voltage of a level high enough to vary the hysteresis characteristics of said pair of MIOS transistors also according to the content of said binary signal; and interrogation means for detecting an output from said read-out line, including means for selectively impressing voltages of different levels respectively on said pair of digit lines according to the content of a binary signal to be interrogated and for impressing at the same time on said word line a voltage of intermediate value between the threshold voltages presented by said hysteresis characteristics varied by said writing means.
Claim 2
Dependent Claim
224 words
An associative memory comprising one bit memory cell including: a pair of MIOS transistors each having a source electrode, a drain electrode, and a gate electrode including double insulating layers and presenting threshold voltage-hysteresis characteristics; a word line connected commonly to the gate electrodes of said pair of MIOS transistors; a pair of digit lines connected respectively to the drain electrodes of said pair of MIOS transistors; a read-out line connected commonly to the source electrodes of said pair of MIOS transisotrs; writing means for writing a binary signal, including means for selectively impressing voltages of different levels respectively on said pair of digit lines according to the content of said binary signal and for selectively impressing at the same time on said word line a negative or positive polarity voltage of a level high enough to vary the hysteresis characteristics of said pair of MIOS transistors also according to the content of said binary signal; and interrogation means for detecting an output from said read-out line, including means for selectively impressing voltages of different levels respectively on said pair of digit lines according to the content of a binary signal to be interrogated and for impressing at the same time on said word line a voltage of intermediate value between the threshold voltages presented by said hysteresis characteristics varied by said writing means.
Claim 3
Dependent Claim
60 words
An associative memory as claimed in claim 1 wherein said pair of MIOS transistors comprise a combination of a p-channel MIOS transistor and an n-channel MIOS transistor and wherein said p-channel and n-channel MIOS transistors present the threshold voltage hysteresis characteristics in the same rotating direction for the voltage impressed on said word line when said writing means is conducted.
Claim 4
Dependent Claim
40 words
An associative memory as claimed in claim 1 wherein one of said pair of MIOS transistors is of the injection type whereas the other is of ion drift type having the same conductivity type as that of said injection type.
Claim 5
Dependent Claim
25 words
An associative memory as claimed in claim 1 wherein each transistor constituting said pair of MIOS transistors has a gate of metal nitride oxide structure.
Claim 6
Dependent Claim
103 words
An associative memory according to claim 1 wherein a plurality of said one bit memory cells are arranged in a matrix, the gate electrodes of said transistors constituting said one bit memory cells in the same row are connected to a common word line, the source electrodes of said transistors are commonly connected to an output line of said associative read-out means, the drain electrodes of one of said two MIOS transistors constituting one bit cells in the same column are commonly connected to one digit line, and the drain electrodes of the other MIOS traNsistor are commonly connected to another digit line.
References Cited (Backward Citations)
US3750115A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-04 | 1978-05-06 | 1978-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-04 | 1982-05-06 | 1982-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-04 | 1986-05-06 | 1986-11-05 | $7700.00 | Window Closed / Lapsed |