US3750115A
Expired / Lapsed
US
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Read mostly associative memory cell for universal logic
Assignee: Harris Intersil Inc
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Filing: 1972-04-28
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Granted: 1973-07-31
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Expires: 1992-04-28
Abstract
Abstract A universal logic system is disclosed wherein arbitrary Boolean functions can be generated by cascading AND and OR logic. The logic system comprises an array of read mostly associative memory cells for storing information determinative of the logic produced. Information is stored in the form of charge, avalanche injected into the gate electrode of floating gate field effect transistors. The AND and OR functions are performed by associative search and read operations respectively. Erasure is performed by avalanche injection from the floating gate to the substrate of the transistor. Voltage variable capacitance elements are included to selectively enhance voltages within the cell.
Inventors
- 👤 J Mundy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:33
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; G11C15/00; G11C15/04; G11C15/046; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
123 words
An associative memory cell comprising: first and second floating gate transistors each having source and drain electrodes, said source electrodes being connected together; a third transistor having first, second and third electrodes, the first electrode thereof being connected to the source electrodes of said first and second transistors; first and second voltage variable capacitance means, each comprising a gate and source electrode structure, having the gates thereof connected to the gates of said first and second floating gate transistors respectively and the sources thereof connected to the third electrode of said third transistor; and four access lines connected one each to the drains of said floating gate transistors, the second electrode of said third transistor and the third electrode of said third transistor.
Claim 2
Dependent Claim
123 words
An associative memory cell comprising: first and second floating gate transistors each having source and drain electrodes, said source electrodes being connected together; a third transistor having first, second and third electrodes, the first electrode thereof being connected to the source electrodes of said first and second transistors; first and second voltage variable capacitance means, each comprising a gate and source electrode structure, having the gates thereof connected to the gates of said first and second floating gate transistors respectively and the sources thereof connected to the third electrode of said third transistor; and four access lines connected one each to the drains of said floating gate transistors, the second electrode of said third transistor and the third electrode of said third transistor.
Claim 3
Dependent Claim
24 words
An associative memory cell as set forth in claim 1 wherein the gate material for said first and second floating gate transistors comprises silicon.
Claim 4
Dependent Claim
24 words
An associative memory cell as set forth in claim 1 wherein the gate material for said first and second floating gate transistors comprises molybdenum.
Claim 5
Dependent Claim
30 words
An associative memory cell as set forth in claim 3 wherein said third transistor is bipolar and said first, second and third electrodes are the emitter, base and collector respectively.
Claim 6
Dependent Claim
30 words
An associative memory cell as set forth in claim 1 wherein said third transistor is bipolar and said first, second and third electrodes are the emitter, base and collector respectively.
Claim 7
Dependent Claim
102 words
An associative memory cell comprising: first, second, third and fourth access lines; first and second floating gate silicon gate transistors, connected respectively to said first and second access lines, for storing information in the form of avalanche injected charge on the gates thereof; a third transistor interconnecting said first and second transistors and said fourth access line, said third access line being connected to a control electrode of said third transistor; and first and second voltage variable capacitance elements, connecting the gates of said first and second transistors respectively with said fourth access line, for enhancing operating voltages within said memory cell.
Claim 8
Dependent Claim
102 words
An associative memory cell comprising: first, second, third and fourth access lines; first and second floating gate silicon gate transistors, connected respectively to said first and second access lines, for storing information in the form of avalanche injected charge on the gates thereof; a third transistor interconnecting said first and second transistors and said fourth access line, said third access line being connected to a control electrode of said third transistor; and first and second voltage variable capacitance elements, connecting the gates of said first and second transistors respectively with said fourth access line, for enhancing operating voltages within said memory cell.
Claim 9
Dependent Claim
27 words
An associative memory cell as set forth in claim 6 wherein said third transistor comprises a field effect transistor and said control electrode comprises the gate thereof.
Claim 10
Dependent Claim
26 words
An associative memory cell as set forth in claim 6 wherein said third transistor comprises a bipolar transistor and said control electrode comprises the base thereof.
Claim 11
Dependent Claim
54 words
An associative memory cell comprising: first, second, third and fourth access lines; first and second fixed impedance devices connecting said first and second access lines to a common point; a bipolar transistor connecting said common point to said fourth access line, said third access line being connected to the base of said bipolar transistor.
Claim 12
Dependent Claim
54 words
An associative memory cell comprising: first, second, third and fourth access lines; first and second fixed impedance devices connecting said first and second access lines to a common point; a bipolar transistor connecting said common point to said fourth access line, said third access line being connected to the base of said bipolar transistor.
Claim 13
Dependent Claim
21 words
An associative memory cell as set forth in claim 9 wherein said first and second fixed impedance elements comprise fusable links.
Claim 14
Dependent Claim
35 words
An associative memory cell as set forth in claim 9 wherein said fixed impedance elements comprise floating gate, molybdenum transistors for storing information in the form of avalanche injected charge on the gate electrode thereof.
Claim 15
Dependent Claim
44 words
An associative memory cell as set forth in claim 11 and further comprising: first and second voltage variable capacitance elements, connecting the gate electrodes of said first and second devices, respectively, to said fourth access line, for enhancing operating voltages within said memory cell.
Claim 16
Independent Claim
83 words
The method of forming arbitrary Boolean functions comprising the steps of: fabricating an array comprising a plurality of read mostly associative memory cells capable of the functions: read, associative search and associative search with mask; storing information in a predeTermined pattern in said array for selectively enabling portions of said cells; applying input information to the array; and sequentially performing read and then search operations to operate on said input information in accordance with the logic determined by the pattern of stored information.
Claim 17
Independent Claim
83 words
The method of forming arbitrary Boolean functions comprising the steps of: fabricating an array comprising a plurality of read mostly associative memory cells capable of the functions: read, associative search and associative search with mask; storing information in a predeTermined pattern in said array for selectively enabling portions of said cells; applying input information to the array; and sequentially performing read and then search operations to operate on said input information in accordance with the logic determined by the pattern of stored information.
Claim 18
Dependent Claim
39 words
The method as set forth in claim 13 and further comprising the step of: masking selected cells in said array for removing the contribution made by said selected cells to the logic function during the time of the mask.
Claim 19
Dependent Claim
36 words
The method as set forth in claim 13 wherein said cells are further capable of writing and said storing step comprises: writing information in a predetermined in said array for selectively enabling portions of said cells.
Claim 20
Dependent Claim
26 words
The method as set forth in claim 13 wherein performing the search operation produces the AND function and performing the read operation produces the OR function.
Claim 21
Dependent Claim
23 words
The method as set forth in claim 13 wherein said applying step comprises: inserting information into the array in an associative search operation.
Claim 22
Dependent Claim
22 words
The method as set forth in claim 13 wherein said applying step comprises: inserting information into the array in a read operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |