US3611319A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically alterable read only memory
Assignee: Teledyne Inc
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Filing: 1969-03-06
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Granted: 1971-10-05
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Expires: 1989-03-06
Abstract
Abstract A memory system is disclosed in which a nonvolatile, write once, nondestructive readout (NDRO) memory array or matrix is accessed by electrical control circuitry, incorporating electronic switches such as silicon-controlled rectifiers (SCR''s). The array includes data-storing cells, typically in the form of diodes, with one cell connected at each junction or nodal point between a word line and a bit line of the array. One binary state is stored in a cell if current can conduct through the cell, while the other binary state is stored if current is permanently inhibited or disrupted from being conducted through the cell. In the write mode, the switches are operated to sequentially select cells, through which a sufficiently high current is supplied until the cell is affected to permanently disrupt the flow of current therethrough. Verification of the storing of any bit is automatically produced. The system further provides a capability of erasing any stored multibit combination, or word, as well as a capability of modifying the content of any word by storing a new word in a spare section of the memory array.
Inventors
- 👤 Gilbert P Hyatt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:34
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
81 words
The arrangement as recited in claim 1 further including third and fourth terminals connected to third and fourth potential levels, n read resistors, each having one end connected to said third terminal and another end connected to one of said bit lines, a word driver for connecting a selected one of said word lines to said fourth terminals and readout means coupled to said n bit lines for sensing the states of the n cells coupled to the selected word line.
Claim 2
Dependent Claim
144 words
The arrangement as recited in claim 1 wherein the gate terminal of each SCR is connected to said bit select means, the potential difference between said first and second potential levels being great enough to produce a sufficient anode to cathode potential drop across said SCR when any of said word lines is substantially at said first potential level, whereby an enabling signal from said bit select means to the gate terminal of an SCR enables the SCR to switch it to its ON state, to enable current to flow through the cell connecting its associated bit line to the selected word line, the disruption of current flow through said cell which is switched to its secOnd state, substantially isolating the SCR from the selected word line, reducing the anode to cathode current therethrough and thereby automatically switching the SCR to its OFF state.
Claim 3
Dependent Claim
105 words
The arrangement as recited in claim 3 wherein each of said x word current gates is an SCR having anode, cathode and gate terminals, with its anode and cathode terminals connected between said first terminal and associated word line, and the gate terminal is connected to said word select means, said arrangement further including bias means coupled to said word lines through said cells to produce a sufficient anode to cathode potential difference across each word SCR, to enable one of the word SCR''s to switch to its ON state when an enabling signal is applied through said word select means to its gate terminal.
Claim 4
Dependent Claim
34 words
The arrangement as recited in claim 4 wherein said bias means include n bias resistors, each having one end connected to said second potential level and the other end to a different bit line.
Claim 5
Dependent Claim
46 words
The arrangement as recited in claim 5 further including write verify means connected to each of said bit lines to provide an indication of the states of the cells connected to said enabled word line as a function of the potential levels at said bit lines.
Claim 6
Dependent Claim
82 words
The arrangement as recited in claim 6 further including third and fourth terminals connected to third and fourth potential levels, n read resistors, each having one end connected to said third terminal and another end connected to one of said bit lines, a word driver for connecting a selected one of said word lines to said fourth terminals and read out means coupled to said n bit lines for sensing the states of the n cells coupled to the selected word line.
Claim 7
Dependent Claim
94 words
The combination as recited in claim 1 including a plurality of substantially identical memory arrays, array-write control means for selecting the array into which a n-bit word is to be stored by controlling the states of a selected group of n cells connected to a selected word line in said selected array, and array-read control means for selecting the array from which the states of all cells coupled to a selected bit line are read out in parallel, with the states of the cells coupled to different bit lines being read out in series.
Claim 8
Dependent Claim
49 words
The combination as recited in claim 8 further including x readout gates, each connected to corresponding word lines in said arrays to provide an output corresponding to the states of a cell connected to its associated word line and the selected bit line in the array selected for readout.
References Cited (Backward Citations)
US3028659A
Cited
US3245051A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-04 | 1975-04-05 | 1975-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-04 | 1979-04-05 | 1979-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-04 | 1983-04-05 | 1983-10-05 | $7700.00 | Window Closed / Lapsed |