Mnos/sos random access memory

Claim 1

In a digital random access memory comprised of a matrix of variable threshold memory cells providing charge enhancement of memory elements during both READ and WRITE modes of operation, a memory cell including: a bistable latch circuit having first and second cross coupled switch devices, said switch devices including a pair of current carrying electrodes and a control electrode; a first load element coupled to one current carrying electrode of said first switch device to define a first circuit node, said first circuit node also being connected to the control electrode of said second switch device; a second and third series connected load element, having a common connection therebetween, coupled to a corresponding one current carrying electrode of said second switch device to define a second circuit node, said second circuit node also being connected to the control electrode of said first switch device; control means selectively operated by a control signal, coupled to said first and second switch devices, rendering both said switch devices inoperative and holding said first and second circuit nodes at a predetermined reference voltage except during said READ and WRITE modes at which time said control means becomes inoperative; a plurality of MNOS memory elements comprised of a substrate, source, drain and gate electrodes, and wherein the respective substrate and source electrodes are commonly connected Together to define a fourth circuit node; a respective plurality of switch devices selectively energized for addressing a respective memory device by coupling the common substrate-source connection of a selected MNOS memory device to said first circuit node; means coupling said gate electrode of said plurality of MNOS memory devices to said common connection between said second and third load elements and defining a third circuit node thereat; said common substrate and source electrode connection defining a fourth circuit node and providing a node capacitance thereat which in combination with the operation of said first load element connected to said first circuit node and the coupling of said fourth circuit node thereat by means of said energized selected switch device during the READ mode is adapted to provide a positive gate to source electrode bias on the addressed memory device and thereby enhance a previously written threshold state of the addressed memory device and also provide a partial charge enhancement of the non-addressed memory elements of said plurality of MNOS memory elements; a fourth load element commonly connected to the drain electrodes of said plurality of MNOS memory devices and defining a fifth circuit node; fifth, sixth and seventh load elements rendered operative by and coupling a memory pulse of predetermined polarity to said first, fifth and third circuit nodes respectively during a portion of said WRITE mode and rendering said first, second and fourth load elements inoperative when rendered operative; third switch means energized by said memory pulse coupled across said third load element and becoming operative thereby to shunt said third load element during said portion of said WRITE mode and to connect said third circuit node directly to said second circuit node; data input means coupled to said second circuit node and being operable during said WRITE mode to couple a predetermined data input signal thereto to set said bistable latch and establish a predetermined threshold state on said selected MNOS memory device; and data output means coupled to said first circuit node and being operable during said READ mode to sense the voltage level thereat, said voltage level being indicative of the previously established threshold state of said selected MNOS memory device.