Non-volatile word-wise electrically reprogrammable store

Claim 1

A non-volatile semiconductor store which can be electrically reprogrammed word-wise, comprising a matrix of storage cells, control means operable to apply voltages to selected storage cells for erasure, write-in and read-out thereof, and monitoring means arranged, in use, to monitor, during an erasure or write in, the state of 100 at least one storage cell and to recognise when the cell, or all the cells, being monitored has reached its erased or, as the case may be, programmed state. 2. A store according to claim 1, in which the monitoring means is arranged, in operation to monitor during erasure the state all the cells of the selected word and during write-in the state of all those cells of the selected word which are to be programmed. 3. A store according to claim 1, in which the store matrix includes an additional storage cell, the control means is arranged to erase or programme the additional cell whenever a selected word is erased or programmed, and the 115 monitoring means is arranged to monitor the state only of the additional cell. 4. A store according to claim 1, in which the store matrix includes an additional storage cell for each word thereof, the control means is arranged 120 to erase or programme the relevant additional cell whenever a selected word is erased or programmed, and the monitoring means is arranged to monitor the state only of the additional cell of the selected word. 5. A store according to any one of claims 1 to 4, in which the control means is arranged in operation to supply erasing voltages to the selected storage cells intermittently in the form of of the cell(s) whilst a voltage equal to said predetermined value is applied to the gates thereof. 9. A store according to any one of claims 1 to 8, in which the control means is arranged in operation to supply programming voltages to the selected storage cell(s) intermittently in the form of pulses, and the monitoring means is arranged to monitor the state of said at least one storage cell during the intervals between the pulses. 10. A store according to any one of claims 1 to 8, in which the control means is arranged in operation to supply programming voltages to the selected storage cell(s) continuously whereby programming and monitoring take place simultaneously. 11. A store according to any one of claims 1 to 10, in which the monitoring means is arranged in operation to recognise programming of the cell(s) being monitored as being complete when. it (they) have a threshold voltage less than or equal to a predetermined value. 12. A store according to claim 11, in which the monitoring means is arranged to monitor the threshold voltage by monitoring the drain voltage of the cell(s) whilst a voltage equal to said predetermined value is applied to the gates thereof. 13. A store according to claim 11 or 12 when dependent on claim 7, including a potential divider arranged to provide a first, lowest predetermined voltage for application to the gates of the seleqted storage cells for monitoring during erasure, a second, highest predetermined voltage for application to the gates of the selected storage cells for monitoring during programming, and a third, intermediate predetermined voltage for application to the gates of the selected storage cells during read-out. 14. A store according to any one of the prec6ding claims, in which the monitoring means is arranged in operation upon said recognition to terminate the application of said voltages by the control means to the cells, thereby terminating the erasure or programming process. 15. A store according to any one of the preceding claims, in which the storage cells are field effect transistors of the floating gate type. 12 GB 2 028 615 A 12 16. A store according to any one of claims 1 to 14, in which the storage cells are field effect transistors constructed in acordance with the MNOS principle. 17. A store according to any one of claims 1 to 16, in which the gate lines of the field effect transistors which are used to construct storage cells run from word to word and the associated drain lines run from bit to bit. 18. A store according to any one of the preceding claims formed as a single integrated circuit. 19. Stores substantially as herein described with reference to the accompanying drawings. Printed for Her Majesty's Stationery Office by the Courier Press. Leamington Spa. 1980. Published by the Patent Office, 25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained. II 2