US5544118A
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Flash EEPROM system cell array with defect management including an error correction scheme
Assignee: SanDisk Technologies LLC
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Filing: 1995-03-07
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Granted: 1996-08-06
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Expires: 2015-03-07
Abstract
Abstract A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occured. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferably as part of the blocks themselves, in order to maintain an endurance history of cells within the block. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
Inventors
- 👤 Eliyahou Harari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:17
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/10; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C11/5642; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0425; G11C16/06; G11C16/34; G11C16/349; G11C16/3495; G11C29/00; G11C29/70; G11C29/76; G11C29/765; G11C29/78; G11C29/80; G11C29/816; G11C29/82; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D64/00; H10D64/01; H10D64/031; H10D64/035; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5613; G11C2211/563; G11C2211/5631; G11C2211/5634; G11C2211/564; G11C2211/5644
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
186 words
In an integrated circuit memory system including an array of non-volatile floating gate memory cells wherein individual cells are addressable for programming and reading their states, a method of operating said memory system, comprising: providing a plurality of distinct blocks of said memory cells, wherein the cells of the individual blocks are erasable together, performing an erase operation upon the memory cells within at least one block, after the erase operation is performed, determining whether there are any unerased cells within said at least one block and, if so, a number of such unerased cells, comparing the number of unerased cells with a permitted number, said permitted number being substantially the maximum number of cells whose data, if bad, are correctable by an error correction scheme, if the number of unerased cells within said at least one block is less than said permitted number, reprogramming memory cells within the erased at least one block with new data, and if the number of unerased cells within said at least one block is greater than said permitted number, substituting other redundant memory cells for the unerased memory cells.
Claim 2
Dependent Claim
186 words
In an integrated circuit memory system including an array of non-volatile floating gate memory cells wherein individual cells are addressable for programming and reading their states, a method of operating said memory system, comprising: providing a plurality of distinct blocks of said memory cells, wherein the cells of the individual blocks are erasable together, performing an erase operation upon the memory cells within at least one block, after the erase operation is performed, determining whether there are any unerased cells within said at least one block and, if so, a number of such unerased cells, comparing the number of unerased cells with a permitted number, said permitted number being substantially the maximum number of cells whose data, if bad, are correctable by an error correction scheme, if the number of unerased cells within said at least one block is less than said permitted number, reprogramming memory cells within the erased at least one block with new data, and if the number of unerased cells within said at least one block is greater than said permitted number, substituting other redundant memory cells for the unerased memory cells.
Claim 3
Dependent Claim
34 words
The method according to claim 1 wherein the substituting step includes determining address locations of the unerased cells within said at least one block, storing said address locations, and substituting redundant good cells therefor.
Claim 4
Dependent Claim
35 words
The method according to claim 1 which additionally comprises, if the number of unerased cells within said at least one block exceeds another number that is significantly larger than said permitted number, raising a flag.
Claim 5
Dependent Claim
90 words
The method according to claim 1 wherein the erase operation is performed as follows: addressing said at least one block and initiating an erase cycle of the memory cells therein, determining the states of the memory cells within said at least one block during the erase cycle, and terminating the erase cycle either when all of the memory cells of said at least one block are determined to be erased or when a predefined condition is reached before all of the cells of said at least one block are erased.
Claim 6
Dependent Claim
36 words
The method according to claim 4 wherein said predefined condition includes reaching a condition where all of the memory cells within said at least one block have been erased except for said permitted number or less.
Claim 7
Dependent Claim
36 words
The method according to claim 1 which additionally comprises incrementing a running count of the number of times that said at least one block has been subjected to an erase cycle, and storing the incremented count.
Claim 8
Dependent Claim
29 words
The method according to claim 6, which additionally comprises, in response to said running count reaching a preset number, substituting a redundant block for said at least one block.
Claim 9
Dependent Claim
35 words
The method according to claim 6, wherein the incremented count is stored within said at least one block after the memory cells within said at least one block have been subjected to the erase cycle.
Claim 10
Dependent Claim
280 words
In an integrated circuit memory system including an array of non-volatile floating gate memory cells wherein individual cells are addressable for programming and reading their states, a method of operating said memory system, comprising: providing a plurality of distinct blocks of said memory cells, wherein the cells of the individual blocks are erasable together to a base state from which one or more of the memory cells within an erased block may be subsequently reprogrammed, addressing at least one of said plurality of blocks and initiating an erase cycle of the memory cells therein, determining the states of the memory cells within said at least one block during the erase cycle, terminating the erase cycle either when all of the memory cells of said at least one block are determined to be erased to the base state or when a predefined condition is reached before all of the cells of said at least one block are erased, if the erase cycle is terminated before all the cells of said at least one block are erased, determining whether the number of unerased memory cells within said at least one block is less than or greater than a permitted number, said permitted number being substantially the maximum number of cells whose data, if bad, are correctable by an error correction scheme, if the number of unerased cells within said at least one block is less than said permitted number, reprogramming memory cells within the erased said at least one block with new data, and if the number of unerased cells within said at least one block is greater than said permitted number, substituting other redundant memory cells for the unerased memory cells.
Claim 11
Dependent Claim
280 words
In an integrated circuit memory system including an array of non-volatile floating gate memory cells wherein individual cells are addressable for programming and reading their states, a method of operating said memory system, comprising: providing a plurality of distinct blocks of said memory cells, wherein the cells of the individual blocks are erasable together to a base state from which one or more of the memory cells within an erased block may be subsequently reprogrammed, addressing at least one of said plurality of blocks and initiating an erase cycle of the memory cells therein, determining the states of the memory cells within said at least one block during the erase cycle, terminating the erase cycle either when all of the memory cells of said at least one block are determined to be erased to the base state or when a predefined condition is reached before all of the cells of said at least one block are erased, if the erase cycle is terminated before all the cells of said at least one block are erased, determining whether the number of unerased memory cells within said at least one block is less than or greater than a permitted number, said permitted number being substantially the maximum number of cells whose data, if bad, are correctable by an error correction scheme, if the number of unerased cells within said at least one block is less than said permitted number, reprogramming memory cells within the erased said at least one block with new data, and if the number of unerased cells within said at least one block is greater than said permitted number, substituting other redundant memory cells for the unerased memory cells.
Claim 12
Dependent Claim
34 words
The method according to claim 9 wherein the substituting step includes determining address locations of the unerased cells within said at least one block, storing said address locations, and substituting redundant good cells therefor.
Claim 13
Dependent Claim
49 words
The method according to claim 9 wherein said predefined condition of the erase cycle includes reaching a condition where all of the memory cells within said at least one block have been erased except for said permitted number or less of memory cells within said at least one block.
Claim 14
Dependent Claim
38 words
The method according to claim 9 wherein the erase cycle comprises application of a plurality of erase pulses to the memory cells within said at least one block with their states being determined in between the erase pulses.
Claim 15
Dependent Claim
26 words
The method according to claim 12 wherein said predefined condition of the erase cycle includes reaching a given number of erase pulses during the erase cycle.
Claim 16
Dependent Claim
38 words
The method according to claim 12 wherein the plurality of erase pulses are increased in magnitude during the erase cycle, and wherein said predefined condition includes when the magnitude of the erase pulses reach a predetermined maximum level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |