Flash eeprom memory systems and methods of using them

Claim 2

1 . A flash electrically erasable and programmable read only memory cell having memory states dictated by the net electronic charge on a floating gate which modulates conductance of a transistor channel, wherein more than two distinct memory states are obtained by providing means for introducing one of more than two given amounts of electronic charge onto said floating gate for indefinite storage until removed by electronic erase, each one of said given amounts corresponding to a different one of said distinct memory states.

Claim 3

The memory cell according to claim 1 wherein said floating gate modulates the transistor channel conductance of only a part of the channel.

Claim 4

For an array of electrically erasable and programmable read only memory cells having means for addressing individual cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, a method of programming a memory state into an addressed cell of the array, comprising the steps of: establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the cell in excess of two, erasing the cell by lowering its effective threshold voltage to a base level that is lower than the lowest of the plurality of detectable states of the cell by positively increasing the charge on the floating gate, and programing the cell to one of its said plurality of states by adding negative charge to its floating gate until its effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels.

Claim 5

For an array of electrically erasable and programmable read only memory cells having means for addressing individual cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, a method of programming a memory state into an addressed cell of the array, comprising the steps of: establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the cell in excess of two, erasing the cell by lowering its effective threshold voltage to a base level that is lower than the lowest of the plurality of detectable states of the cell by positively increasing the charge on the floating gate, and programing the cell to one of its said plurality of states by adding negative charge to its floating gate until its effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels.

Claim 6

The method of claim 3 wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels, whereby the cell can store at least two bits of information.

Claim 7

The method of claim 4 wherein the threshold voltage level establishing step includes selecting at least two of said plurality of effective threshold voltage levels to be less than said natural threshold voltage level of the cell transistor.

Claim 8

The method of claim 3 wherein the step of programming the cell to any one of its said plurality of threshold voltage levels includes alternately pulsing the cell with short programming pulses and reading a current therethrough after each such programming pulse until the current level reaches that corresponding to the desired one of said plurality of effective threshold levels, each one of said short programming pulses being insufficient to change said effective threshold voltage by more than approximately one-half of the difference between any two adjacent of said plurality of threshold voltage levels.

Claim 9

The method of claim 3 wherein the step of erasing the cell includes alternately pulsing the cell with an erase pulse and reading a current therethrough until the current level reaches that corresponding to the desired base threshold level, the magnitude and duration of each such erase pulse being chosen so that the first erase pulse is insufficient to fully erase said cell and each subsequent erase pulse has its magnitude increased by a fixed increment until the cell is fully erased.

Claim 10

The method of claim 7 which comprises the additional step of, after the cell has been erased to its base threshold level, incrementing a counter by one, thereby allowing the total number of times the cell has been erased to be monitored.

Claim 11

The method of claim 7 wherein the step of erasing the cell additionally includes discontinuing the erase pulses after a predetermined number of erase pulses has been applied.

Claim 12

For an array of electrically erasable and programable read only memory cells having means for addressing individual cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, first and second memory states corresponding to first and second effective threshold voltages, respectively, a method of programming an addressed cell of the array into the first or second state, comprising the steps of: pulsing said addressed cell for a predetermined time and voltage sufficient to alter the charge on its floating gate and change its effective threshold voltage but insufficient to change the effective threshold voltage by more that approximately one-half the difference between the said first and second effective threshold voltages, thereafter reading the current through the addressed cell to determine whether the effective threshold voltage has reached the new desired first or second state, and repeating the pulsing and reading steps until a desired first or second memory state of the addressed cell is detected by the reading step, at which time the programming of the addressed cell is completed.

Claim 13

For an array of electrically erasable and programable read only memory cells having means for addressing individual cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, first and second memory states corresponding to first and second effective threshold voltages, respectively, a method of programming an addressed cell of the array into the first or second state, comprising the steps of: pulsing said addressed cell for a predetermined time and voltage sufficient to alter the charge on its floating gate and change its effective threshold voltage but insufficient to change the effective threshold voltage by more that approximately one-half the difference between the said first and second effective threshold voltages, thereafter reading the current through the addressed cell to determine whether the effective threshold voltage has reached the new desired first or second state, and repeating the pulsing and reading steps until a desired first or second memory state of the addressed cell is detected by the reading step, at which time the programming of the addressed cell is completed.

Claim 14

For an array of a plurality of electrically erasable and programable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, a method of erasing a memory state from an addressed group of cells of the array, comprising the steps of: pulsing the addressed cells for a predetermined time and voltage sufficient to alter the threshold voltage but insufficient to completely erase said cells, thereafter reading the current through the addressed cells in order to ascertain their altered threshold levels, and repeating the pulsing and reading steps a plurality of times, each repeat of the pulsing step increasing the voltage an increment above that of the last pulsing step.

Claim 15

For an array of a plurality of electrically erasable and programable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, a method of erasing a memory state from an addressed group of cells of the array, comprising the steps of: pulsing the addressed cells for a predetermined time and voltage sufficient to alter the threshold voltage but insufficient to completely erase said cells, thereafter reading the current through the addressed cells in order to ascertain their altered threshold levels, and repeating the pulsing and reading steps a plurality of times, each repeat of the pulsing step increasing the voltage an increment above that of the last pulsing step.

Claim 16

The memory erasing method according to claim 11 which comprises the additional step of accumulating a count equal to a total number of times that cell has been erased.

Claim 17

The memory erasing method according to claim 11 wherein the repeating pulsing and reading steps is terminated upon the first occurance of any one of conditions of: the threshold level of each of the addressed cells has reached an erased state; or a predetermined number of erase pulses has been applied; or a predetermined maximum voltage of the erase pulse has been reached; or the number of the addressed cells which remain not fully erased has declined below a predetermined acceptable number of unerased cells.

Claim 18

In an array of a plurality of electrically erasable and programable read only memory cells wherein each cell includes a split-channel field effect transistor that has in a semiconductor substrate a source and drain separated by a channel region, a floating gate positioned over only a portion of and insulated from the channel region adjacent the drain, and a control gate extending over and insulated from the floating gate and another portion of the channel adjacent the source, said transistor having a first portion with a natural threshold voltage that is alterable by controlling a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, the conductance of said first transistor portion being determined by a voltage on the control gate and the level of charge on the floating gate, and said transistor having a second portion in series with said first portion that has a conductance determined by a voltage on said control gate, a system for erasing, programming and reading the memory state of the cells in said array, comprising: means operably connected to said array for addressing a selected one or group of the plurality of memory cells, erasing means operably connected to said array for lowering the effective threshold voltage of an addressed cell or group of cells to a base level by positively increasing the charge on each cell's floating gate, programming means operably connected to said array for adding negative charge to the floating gate of an addressed cell until its effective threshold voltage is substantially equal to one of a plurality of effective threshold voltage levels in excess of two, whereby each cell of the array is programmable into one of a corresponding number of states in excess of two, and reading means operably connected to said array for determining the amount of current that flows in an addressed cell, wherein a number of individually detectable current levels correspond to the number of effectice threshold voltage levels, whereby the state of an addressed cell is determined from its measured current level.

Claim 19

In an array of a plurality of electrically erasable and programable read only memory cells wherein each cell includes a split-channel field effect transistor that has in a semiconductor substrate a source and drain separated by a channel region, a floating gate positioned over only a portion of and insulated from the channel region adjacent the drain, and a control gate extending over and insulated from the floating gate and another portion of the channel adjacent the source, said transistor having a first portion with a natural threshold voltage that is alterable by controlling a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, the conductance of said first transistor portion being determined by a voltage on the control gate and the level of charge on the floating gate, and said transistor having a second portion in series with said first portion that has a conductance determined by a voltage on said control gate, a system for erasing, programming and reading the memory state of the cells in said array, comprising: means operably connected to said array for addressing a selected one or group of the plurality of memory cells, erasing means operably connected to said array for lowering the effective threshold voltage of an addressed cell or group of cells to a base level by positively increasing the charge on each cell's floating gate, programming means operably connected to said array for adding negative charge to the floating gate of an addressed cell until its effective threshold voltage is substantially equal to one of a plurality of effective threshold voltage levels in excess of two, whereby each cell of the array is programmable into one of a corresponding number of states in excess of two, and reading means operably connected to said array for determining the amount of current that flows in an addressed cell, wherein a number of individually detectable current levels correspond to the number of effectice threshold voltage levels, whereby the state of an addressed cell is determined from its measured current level.

Claim 20

The memory array erasing, programming and reading system according to claim 14 wherein said array of memory cells includes a common connection between the control gates of memory cells in a row, and wherein said programming means additionally includes means for applying said first high positive voltage to said common connection of a row of cells and for applying said second high positive voltage to only the drains of those memory cells in said row which have not yet reached their desired particular programmed effective threshold voltage level.

Claim 21

In an electrically erasable and programmable read only memory system, comprising: a semiconductor substrate including an array of a plurality of storage cells in rows and columns, each cell containing a transistor that includes: a source region and a drain region with a channel therebetween, a floating gate whose level of charge affects the level of conductance between the source and drain, a control gate whose electrical potential affects the level of conductance between the source and drain, column means connectable to an addressed column of said storage cell transisors for controlling a voltage applied to the source and drain regions of the cells therein, row means connectable to an addressed row of said storage cell transistors for controlling the potential level of the control gates of the cells therein, programming means responsive to an address of a particular cell for causing the column means and row means to apply voltages to the addressed cell to increase the electron charge on its floating gate, thereby to decrease the conductance of the addressed cell transistor, reading means responsive to said column means impressing a voltage across the source and drain connections of an addressed column and to the row means increasing the potential level of the control gates of an addressed row for detecting the level of current flow between the source and drain of an addressed cell, thereby determining its state, and erasing means connected with the storage cells of the array for removing electrical charge from the floating gates of a plurality of storage cell transistors, the improvement comprising: said reading means including means for discriminating between a plurality of more than two current ranges of the addressed cell, each cell thereby having a corresponding plurality of states more than two, and said programming means including means responsive to said reading means for causing said column means and said row means to apply programming voltages to an addressed cell to increase the electron charge on its floating gate until the read current flowing in the addressed cell is within one of the more than two current ranges.

Claim 22

In an electrically erasable and programmable read only memory system, comprising: a semiconductor substrate including an array of a plurality of storage cells in rows and columns, each cell containing a transistor that includes: a source region and a drain region with a channel therebetween, a floating gate whose level of charge affects the level of conductance between the source and drain, a control gate whose electrical potential affects the level of conductance between the source and drain, column means connectable to an addressed column of said storage cell transisors for controlling a voltage applied to the source and drain regions of the cells therein, row means connectable to an addressed row of said storage cell transistors for controlling the potential level of the control gates of the cells therein, programming means responsive to an address of a particular cell for causing the column means and row means to apply voltages to the addressed cell to increase the electron charge on its floating gate, thereby to decrease the conductance of the addressed cell transistor, reading means responsive to said column means impressing a voltage across the source and drain connections of an addressed column and to the row means increasing the potential level of the control gates of an addressed row for detecting the level of current flow between the source and drain of an addressed cell, thereby determining its state, and erasing means connected with the storage cells of the array for removing electrical charge from the floating gates of a plurality of storage cell transistors, the improvement comprising: said reading means including means for discriminating between a plurality of more than two current ranges of the addressed cell, each cell thereby having a corresponding plurality of states more than two, and said programming means including means responsive to said reading means for causing said column means and said row means to apply programming voltages to an addressed cell to increase the electron charge on its floating gate until the read current flowing in the addressed cell is within one of the more than two current ranges.

Claim 23

The improved memory system of claim 16 which additionally includes means for accumulating a count of the number of times that said plurality of storage cell transistors has been erased.

Claim 24

The improved memory system of claim 16 wherein said reading means additionally includes at least one differential sense amplifier connectable to the drain of an addressed cell, wherein more than two reference levels are provided to said differential sense amplifier, thereby to establish the more than two programmable conductance levels for each of the addressable cells.

Claim 25

The improved memory system of claim 16 wherein said erasing means includes the additional improvement of means operably connected to said row means and said column means for repeating a cycle of applying an erase voltage in a short erase pulse and then reading the addressed cell current, the initial voltage level of the erase pulse chosen to be insufficient to fully erase the cell and increasing an incremental amount from pulse to pulse, said pulses continuing until the cell current has been increased to a desired base level, whereby the cell has been fully erased.

Claim 26

The improved memory system of claim 19 wherein said erasing means operates to repeat erase cycles only until the first occurance of any one of the following conditions: (1) the threshold level of each of the addressed cells has reached the base level for a fully erased state; or (2) a predetermined number of erase pulses has been applied; or (3) a predetermined maximum voltage of the erase pulse has been reached; or (4) the number of the addressed cells which remain not fully erased has declined below a predetermined acceptable number of cells which are not fully erased.

Claim 27

21 . The improved memory system of claim 16 wherein said transistor floating gate affects the level of conductance between only a first portion of the channel between the source and drain regions, and wherein the level of conductance in a second portion of the channel between the source and drain regions is determined by a voltage on the control gate.