Electrically alterable n-bit per cell non-volatile memory with reference cells

Claim 1

An electrically alterable non-volatile memory comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including a plurality of reference cells, each reference cell having the same characteristic as that of the transistor of each of said memory cell, said plurality of reference cells being arranged in a plurality of rows corresponding to the respective rows in which said plurality of memory cells are arranged such that each row of reference cells includes one reference cell set to each of the different threshold voltages; first selecting means for selecting one of said memory cells; second selecting means for selecting the reference cells arranged in one of said rows corresponding to said one of said memory cells selected by said first selecting means; comparing means for comparing a memory current read out of the selected memory cell with a reference current read out of each of the selected reference cells, sequentially in an order of levels of the threshold voltages set for the selected reference cells, respectively, thereby outputting data according to such comparison; source and bit lines connected to sources and drains, respectively, of the transistors provided to the respective memory cells arranged in each of the columns; a word line connected to gates of the transistors of the memory cells arranged in each of the rows; circuit means for writing data into said memory, said circuit means comprising means for applying to the word line connected to the gate of the transistor of the selected memory cell a pulse signal having a predetermined voltage value under a condition that the source line connected to the source of the transistor provided to the selected memory cell is at an open state, while applying to the bit line connected to the drain of the transistor provided to the selected memory cell a voltage corresponding to one of said different threshold voltages selected depending on the data to be written into said memory; and switching means connected to the source line associated with the memory cells arranged in each of said columns for selectively switching said source line between the open state and a ground potential.