US5012448A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier for a ROM having a multilevel memory cell
Assignee: Ricoh Co Ltd
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Filing: 1988-07-15
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Granted: 1991-04-30
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Expires: 2008-07-15
Abstract
Abstract A multilevel sense circuit includes a memory MOSFET having one of at least two different current carrying states and a pair of reference MOSFETs one of which has one of the two current carrying states and the other of which has the other current carrying state. A first current supplying circuit is connected to the memory MOSFET for supplying a predetermined amount of current thereto when the memory MOSFET is activated. A second current supplying circuit is connected to the pair of reference MOSFETs and also to the first current supplying circuit, such that twice the aforementioned predetermined amount of current is supplied to the pair of reference MOSFETs when the memory MOSFET is activated. A multilevel semiconductor memory device includes a MOSFET having a channel whose width is varyingly set by providing a non-inverting region in a selected area of the channel by ion implantation.
Inventors
- 👤 Shigeki Matsuoka
- 👤 Hiizu Okubo
- 👤 Daisuke Kosaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C11/5692; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C7/00; G11C7/14; H; H10; H10B; H10B20/00; G11C2211/00; G11C2211/56; G11C2211/563; G11C2211/5634; G11C7/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
209 words
A sense circuit comprising: at least one multilevel memory transistor having one of at least first and second possible memory states which are identifiable by respective first and second levels of current flowing therethrough, respectively, said at least one memory transistor including a first terminal for receiving a first activation signal, a second terminal connected to a first node and a third terminal connected to a first reference potential; at least a pair of first and second reference transistors which pass current having said first and second levels, respectively, under the same biasing condition as that of said memory transistor, each of said reference transistors including a first terminal for receiving a second activation signal, a second terminal connected to a second node and a third terminal connected to said first reference potential; first current supplying means connected between said first node and a second reference potential for supplying a predetermined amount of current to said memory transistor when said first activation signal is supplied; and second current supplying means connected between said second node and said second reference potential and also connected to said first current supplying means for supplying approximately twice said predetermined amount of current to said reference transistors when said second activation signal is supplied.
Claim 2
Dependent Claim
209 words
A sense circuit comprising: at least one multilevel memory transistor having one of at least first and second possible memory states which are identifiable by respective first and second levels of current flowing therethrough, respectively, said at least one memory transistor including a first terminal for receiving a first activation signal, a second terminal connected to a first node and a third terminal connected to a first reference potential; at least a pair of first and second reference transistors which pass current having said first and second levels, respectively, under the same biasing condition as that of said memory transistor, each of said reference transistors including a first terminal for receiving a second activation signal, a second terminal connected to a second node and a third terminal connected to said first reference potential; first current supplying means connected between said first node and a second reference potential for supplying a predetermined amount of current to said memory transistor when said first activation signal is supplied; and second current supplying means connected between said second node and said second reference potential and also connected to said first current supplying means for supplying approximately twice said predetermined amount of current to said reference transistors when said second activation signal is supplied.
Claim 3
Dependent Claim
92 words
The sense circuit of claim 1 wherein said first current supplying means includes: a first MOS transistor having a first source/drain connected to said first node and a second source/drain connected to a third node and including a gate; a first inverter having an output connected to said gate of said first transistor and an input connected to said first node; and a second MOS transistor having a first source/drain connected to said third node, a second source/drain connected to said second reference potential and a gate connected to said third node.
Claim 4
Dependent Claim
96 words
The sense circuit of claim 2 wherein said second current supplying means includes: a third MOS transistor having a first source/drain connected to said second node and a second source/drain connected to a fourth node and including a gate; a second inverter having an output connected to said gate of said third transistor and an input connected to said second node; and a pair of fourth and fifth MOS transistors, having a first source/drain connected to said fourth node, a second source/drain connected to said second reference potential and a gate connected to said third node.
Claim 5
Dependent Claim
24 words
The sense circuit of claim 3 wherein said first reference potential is ground potential and said second reference potential is a power supply potential.
Claim 6
Dependent Claim
18 words
The sense circuit of claim 4 wherein each of said memory and reference transistors is an MOS transistor.
Claim 7
Dependent Claim
16 words
The sense circuit of claim 4 wherein said first and third MOS transistors and N-channel MOSFETs.
Claim 8
Dependent Claim
24 words
The sense circuit of claim 6 wherein said second, fourth and fifth MOS transistors are all P-channel MOSFETs having substantially the same transistor characteristics.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |