Multi-bit read only memory circuit

Claim 2

A read only memory (ROM) circuit, comprising: a word line; a plurality of storage transistors having the control terminals thereof connected to said word line, each of said storage transistors having one of a plurality of threshold voltages wherein said threshold voltages correspond to respective predetermined data states; a plurality of reference transistors having the control terminals thereof connected to said word line, each of said reference transistors having one of said threshold voltages; means for driving each of said transistors to an initial condition; means for generating a control signal which is applied to each of said transistors for sequentially driving a plurality of said transistors from said initial condition to a final condition in an order corresponding to the threshold voltages of said transistors; means for determining the condition, initial or final, of said reference transistors when a selected one of said storage transistors is driven from said initial condition to said final condition; and means for decoding the condition, initial or final, determined for said reference transistors when said selected storage transistor is driven to said final condition to generate an output signal corresponding to the data state of said selected storage transistor.

Claim 3

The ROM circuit recited in claim 1 including an additional storage transistor having a threshold sufficiently high such that said additional storage transistor cannot be driven to said final condition.

Claim 4

The ROM circuit recited in claim 1 wherein said means for generating a control signal functions in response to changes in condition of said reference transistors to generate said control signal having a plurality of sequential voltage steps.

Claim 5

The ROM circuit recited in claim 3 wherein each of said sequential voltage steps corresponds to one of said threshold voltages.

Claim 6

The ROM circuit recited in claim 1 including means for delaying the operation of said means for determining the state of said reference transistors relative to the change in condition of said selected storage transistor.

Claim 7

The ROM circuit recited in claim 1 wherein said reference transistors are positioned at one end of said word line.

Claim 8

A read only memory (ROM) circuit, comprising: a word line; a plurality of data storage transistors having the gate terminals thereof connected to said word line, each of said storage transistors having one of a plurality of threshold voltages wherein each said threshold voltage corresponds to a respective predetermined data state; a plurality of reference transistors having the gate terminals thereof connected to said word line, each of said reference transistors fabricated to have a different one of said threshold voltages; means for precharging the source and drain nodes of said transistors; means for driving said word line from a first voltage state to a second voltage state; means for applying a control signal to a first of the source and drain terminals of said transistors wherein said control signal comprises a series of voltage steps which sequentially increase the control voltage applied to turn on said transistors, said control signal causing said reference transistors to be sequentially turned on in order of the threshold voltages of said reference transistors; means for determining the on/off states of said reference transistors when a selected one of said data storage transistors is turned on to produce an output signal corresponding to the predetermined data state for said selected storage transistor.

Claim 9

A read only memory (ROM) circuit, comprising: a word line; a plurality of data storage transistors having the gate terminals thereof connected to said word line, each of said storage transistors having one of a plurality of threshold voltages wherein each said threshold voltage corresponds to a respective predetermined data state; a plurality of reference transistors having the gate terminals thereof connected to said word line, each of said reference transistors fabricated to have a different one of said threshold voltages; means for precharging the source and drain nodes of said transistors; means for driving said word line from a first voltage state to a second voltage state; means for applying a control signal to a first of the source and drain terminals of said transistors wherein said control signal comprises a series of voltage steps which sequentially increase the control voltage applied to turn on said transistors, said control signal causing said reference transistors to be sequentially turned on in order of the threshold voltages of said reference transistors; means for determining the on/off states of said reference transistors when a selected one of said data storage transistors is turned on to produce an output signal corresponding to the predetermined data state for said selected storage transistor.

Claim 10

The ROM circuit recited in claim 7 wherein each of said data storage transistors are fabricated to have one of four threshold voltages thereby storing two data bits per storage transistor and wherein there are three of said reference transistors for each of said word lines, each one of said reference transistors on said word line having a different one of three of said four threshold voltages.

Claim 11

The ROM circuit recited in claim 7 wherein said step signal has three step voltages comprising a first step voltage having an amplitude to render conductive the ones of said transistors having a first of said four threshold voltages, a second voltage step having an amplitude to render conductive the ones of said transistors having the first and a second of said four threshold voltages, and a third voltage step having an amplitude to render conductive the ones of said transistors having the first, the second and a third of said four threshold voltages.

Claim 12

The ROM circuit recited in claim 7 wherein said means for determining comprises a group of three latches connected to receive signals which indicate respectively the states of said reference transistors, said latches set when said selected storage transistor is turned on or the corresponding reference transistor is turned on, and means for decoding the states of said latches when set to produce an output signal which indicates the condition of said selected storage transistor.

Claim 13

The ROM circuit recited in claim 7 wherein said means for generating a control signal functions to generate said control signal in response to the sequential turn-on of said reference transistors.

Claim 14

The ROM circuit recited in claim 7 including means for time delaying the indication of turn-on of each of said reference transistors in relation to a one of said storage transistors having the same threshold voltage.

Claim 15

A read only memory (ROM) circuit, comprising: a word line; a plurality of data storage transistors having the gate terminals thereof connected to said word line, each of said storage transistors having one of four threshold voltages wherein each of said threshold voltages corresponds to a data state; a group of three reference transistors having the gate terminals thereof connected to said word line, each of said reference transistor having a different one of said threshold voltages; circuit means for precharging the source and drain terminals for said transistors; a control signal line for said transistors; a data line corresponding to said storage transistors; a plurality of column select transistors each connected between said control signal line and the source terminal for a respective one of said transistors for selectively connecting the corresponding transistor to said control signal line in response to a memory address signal; a plurality of data transfer transistors each connected between said data line and the drain terminal for a respective one of said storage transistors for selectively connecting the corresponding storage transistor to said data line in response to a memory address signal; a reference data transistor for each of said reference transistors, each reference data transistor having the drain terminal thereof connected to the drain terminal of a respective one of said reference transistors, the gate terminals of said reference data transistors connected to receive a memory address signal; a first comparator having a first input thereof connected to said data line and a second input thereof connected to receive a first reference voltage; a second comparator having a first input thereof connected to the source terminal of a first of said reference data transistors and a second input thereof connected to receive a second reference voltage; a third comparator having a first terminal thereof connected to the source terminal of a second of said reference data transistors and a second terminal thereof connected to receive said second reference voltage; a fourth comparator having a first input thereof connected to the source terminal of a third of said reference data transistors and a second input thereof connected to receive said second reference voltage; a first latch which is set by the output signal from said first comparator or by the output signal from said second comparator to latch the state of the output signal received from said second comparator; a second latch which is set by the output signal from said first comparator or by the output signal from said third comparator to latch the state of the output signal received from said third comparator; a third latch which is set by the output signal from said first comparator or by the output signal received from said fourth comparator to latch the state of the output signal received from said fourth comparator; a control signal circuit for generating a multi-step control signal which is transmitted through said control line to said transistors following receipt of a word line signal on said word line, said control signal having a first voltage step for rendering conductive the ones of said transistors having a first of said threshold voltages, a second voltage step for rendering conductive the ones of said transistors having the first and a second of said voltage thresholds and a third voltage step for rendering conductive the ones of said transistors have the first, the second and a third of said voltage thresholds, said second and third voltage steps generated in response to the output signals from said second and said third comparators; and circuit means connected to decode the output of said latches for generating an output signal which corresponds to the data state of an addressed one of said storage transistors.

Claim 16

A read only memory (ROM) circuit, comprising: a word line; a plurality of data storage transistors having the gate terminals thereof connected to said word line, each of said storage transistors having one of four threshold voltages wherein each of said threshold voltages corresponds to a data state; a group of three reference transistors having the gate terminals thereof connected to said word line, each of said reference transistor having a different one of said threshold voltages; circuit means for precharging the source and drain terminals for said transistors; a control signal line for said transistors; a data line corresponding to said storage transistors; a plurality of column select transistors each connected between said control signal line and the source terminal for a respective one of said transistors for selectively connecting the corresponding transistor to said control signal line in response to a memory address signal; a plurality of data transfer transistors each connected between said data line and the drain terminal for a respective one of said storage transistors for selectively connecting the corresponding storage transistor to said data line in response to a memory address signal; a reference data transistor for each of said reference transistors, each reference data transistor having the drain terminal thereof connected to the drain terminal of a respective one of said reference transistors, the gate terminals of said reference data transistors connected to receive a memory address signal; a first comparator having a first input thereof connected to said data line and a second input thereof connected to receive a first reference voltage; a second comparator having a first input thereof connected to the source terminal of a first of said reference data transistors and a second input thereof connected to receive a second reference voltage; a third comparator having a first terminal thereof connected to the source terminal of a second of said reference data transistors and a second terminal thereof connected to receive said second reference voltage; a fourth comparator having a first input thereof connected to the source terminal of a third of said reference data transistors and a second input thereof connected to receive said second reference voltage; a first latch which is set by the output signal from said first comparator or by the output signal from said second comparator to latch the state of the output signal received from said second comparator; a second latch which is set by the output signal from said first comparator or by the output signal from said third comparator to latch the state of the output signal received from said third comparator; a third latch which is set by the output signal from said first comparator or by the output signal received from said fourth comparator to latch the state of the output signal received from said fourth comparator; a control signal circuit for generating a multi-step control signal which is transmitted through said control line to said transistors following receipt of a word line signal on said word line, said control signal having a first voltage step for rendering conductive the ones of said transistors having a first of said threshold voltages, a second voltage step for rendering conductive the ones of said transistors having the first and a second of said voltage thresholds and a third voltage step for rendering conductive the ones of said transistors have the first, the second and a third of said voltage thresholds, said second and third voltage steps generated in response to the output signals from said second and said third comparators; and circuit means connected to decode the output of said latches for generating an output signal which corresponds to the data state of an addressed one of said storage transistors.

Claim 19

The method recited in claim 14 wherein said control signal is generated in response to a change of condition of said reference transistors.

Claim 20

The method recited in claim 14 wherein predetermined ones of said data storage transistors having a selected one of said threshold voltages are not driven to said final state by said control signal said predetermined ones of said data storage transistors decoded after all of said reference transistors have been driven to said final condition.

Claim 21

The method recited in claim 14 wherein said transistors in said initial condition are turned off and said transistors in said final condition are turned on.

Claim 22

The method recited in claim 14 wherein the step of applying a control signal to each of said transistors comprises applying a stepwise increasing gate to source voltage to said transistors wherein each voltage step of said control signal is a function of said threshold voltages.

Claim 23

The method recited in claim 14 including the step of delaying the indication of change in condition for each of said reference transistors.

Claim 26

The method recited in claim 20 wherein said first and second reference voltages are different thereby time offsetting the transition of said data state signal and said reference data signal for corresponding one of said storage and reference transistors having the same threshold voltage.

Claim 27

The method recited in claim 20 wherein at least one of the voltage steps of said control signal are generated in response to a transition of one of said reference data state signals.