EP0035646A2
Expired / Lapsed
EP
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Integrated semiconductor memory matrix using one-FET cells
Assignee: International Business Machines Corp
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Filing: 1981-02-05
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Granted: —
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Expires: 2001-02-05
Abstract
Abstract A storage system, such as a read only memory, is provided which includes field effect transistors (54, 56) each having first and second spaced apart diffusion regions (38,40; 46, 48) of a given conductivity and a gate electrode (28,30), with at least one of the two diffusion regions of selected transistors having a third diffusion (42,44) adjacent to one of the first and second diffusion regions (38, 40; 46,48) under the gate electrodes (28, 30) to provide a higher voltage threshold for the gate electrode to one diffusion than for the gate electrode to the other of the two diffusions. A voltage is applied to the first diffusion (38) having a polarity and magnitude sufficient to neutralize or eliminate the effects of the higher threshold during a first time period and the current flowing between the first and second diffusions (38,40; 46,48) is sensed. During a second period of time the voltage is applied to the second diffusion (46, 48) and the current flow between the first and second diffusions (38, 40; 46, 48) is again sensed. In this manner two cells or bits of information are stored in each transistor (54, 56), one at the first diffusion (38) and one at the second diffusion (48). Multilevel storing may also be employed by establishing one of more than two predetermined voltage thresholds at each of the first and second diffusions.
Inventors
- 👤 Wilbur David Pricer
- 👤 James Earl Selleck
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 18:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/56; G11C11/5692
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
115 words
Integrated semiconductor storage or transistor.array with field effect transistor cells between rows and columns, characterized by a field effect transistor (54, 56) having a gate electrode (28, 30) and first and second spaced apart diffusions (38, 40; 46, 48), at least one of said diffusions with said gate electrode having one of at least two different predetermined voltage thresholds, means (42, 44) for applying a voltage to said one diffusion having a polarity and magnitude sufficient to neutralize the highest of said at least two predetermined voltage thresholds during a given time period, and means (51A, 51B) for sensing current flow between said spaced apart diffusions (38, 40; 46, 48) during said given time period.
Claim 2
Dependent Claim
115 words
Integrated semiconductor storage or transistor.array with field effect transistor cells between rows and columns, characterized by a field effect transistor (54, 56) having a gate electrode (28, 30) and first and second spaced apart diffusions (38, 40; 46, 48), at least one of said diffusions with said gate electrode having one of at least two different predetermined voltage thresholds, means (42, 44) for applying a voltage to said one diffusion having a polarity and magnitude sufficient to neutralize the highest of said at least two predetermined voltage thresholds during a given time period, and means (51A, 51B) for sensing current flow between said spaced apart diffusions (38, 40; 46, 48) during said given time period.
Claim 3
Dependent Claim
122 words
Integrated semiconductor storage or transistor array with field effect transistor cells between rows and columns, characterized by a field effect transistor (54, 56) having a gate electrode (28, 30) and first and second spaced apart diffusions (38, 40; 46, 48), said first diffusion (38) with said gate electrode (28, 30) having a given voltage threshold and said second diffusion (40) with said gate electrode having a lower voltage threshold than that of said given voltage threshold, means (42) for applying a voltage to said first diffusion (38) having a polarity and magnitude sufficient to neutralize said given voltage threshold during a given time period, and means for sensing (51A, 51B) current flow between said spaced apart diffusions during said given time period.
Claim 4
Dependent Claim
122 words
Integrated semiconductor storage or transistor array with field effect transistor cells between rows and columns, characterized by a field effect transistor (54, 56) having a gate electrode (28, 30) and first and second spaced apart diffusions (38, 40; 46, 48), said first diffusion (38) with said gate electrode (28, 30) having a given voltage threshold and said second diffusion (40) with said gate electrode having a lower voltage threshold than that of said given voltage threshold, means (42) for applying a voltage to said first diffusion (38) having a polarity and magnitude sufficient to neutralize said given voltage threshold during a given time period, and means for sensing (51A, 51B) current flow between said spaced apart diffusions during said given time period.
Claim 5
Dependent Claim
67 words
A storage or transistor array according to claim 1 and 2, characterized by a plurality of field effect transistors (54, 56), each having two different predetermined voltage thresholds, means (42, 44) for neutralizing the highest of said voltage thresholds of at least some of said transistors during a given time period, and means (51A, 51B) for sensing current flow through said transistors during said given time period.
Claim 6
Dependent Claim
39 words
A storage or transistor array according to claim 1-3, wherein voltage applying means applies said voltage to each of said second diffusions during a second time period and said current sensing means senses current during said second time period.
Claim 7
Dependent Claim
119 words
A storage or transistor array according to claim 1-4, characterized by a field effect transistor having a gate electrode (28, 30) and first and second spaced apart diffusions (38, 40; 46, 48) of a first conductivity type (N+) and a third diffusion (42, 44) of a second conductivity type (P+) disposed adjacent to one of said first and second diffusions under said gate electrode (28, 30), means (42) for applying a voltage to said one diffusion having a polarity and magnitude sufficient to eliminate the voltage threshold effects of said third diffusion on said transistor during a given time period, and means (51A, 51B) for sensing current flow between said first and second diffusions during said given time period.
Claim 8
Dependent Claim
151 words
A storage or transistor array according to claim 1-5, characterized by a field effect transistor (54, 56) having first and second spaced apart diffusions (38, 40; 46, 48) of a first conductivity type, a gate electrode (28, 30) disposed between said diffusions and a third diffusion (42, 44) of an opposite conductivity type disposed adjacent to said first diffusion under said gate electrode, means (T20, T14) for applying a voltage to said first diffusion having a polarity and magnitude sufficient to eliminate the voltage threshold effects of said third diffusion on said transistor during a first time period, first means (51A) for determining current flow between said first and second diffusions during said given time period, means (T14, T20) for applying said voltage to said second diffusion during a second time period, and second means (51B) for determining current flow between said first and second diffusions during said second time period.
Claim 9
Dependent Claim
45 words
A storage or transistor array according to claim 1 and 6, wherein said first means determines current tending to flow from said first diffusion to said second diffusion and said second means determines current tending to flow from said second diffusion to said first diffusion.
Claim 10
Dependent Claim
32 words
A storage or transistor array according to claim 1-7, wherein said first conductivity type is N+ type and said opposite conductivity type is P+ type and said voltage is a positive voltage.
Claim 11
Dependent Claim
42 words
A storage or transistor array according to claim 1-8, wherein said first current determining means includes a first sense amplifier coupled to said first diffusion and wherein said second current determining means includes a second sense amplifier coupled to said second diffusion.
Claim 12
Dependent Claim
204 words
A storage or transistor array according to claim 1-9, characterized by an array of field effect transistors (54, 56), each transistor having first and second diffusions (38, 40; 46, 48) of a first conductivity type and a gate electrode (28, 30; and means (42, 44) for providina different voltage thresholds between said gate electrode and said first diffusion and said gate electrode and said second diffusion at selected transistors of said array, first means including bit sense lines (39, 41) for charging said first diffusion to a first voltage having a polarity and magnitude sufficient to eliminate the highest of said voltage thresholds between said gate electrode and said first diffusion and for grounding said second diffusion during a first time period, and second means including a word line (24, 24') connected to said gate electrodes having a second voltage applied thereto and sense amplifiers coupled between said first and second diffusions of said transistors for determining current flow through said transistors during said first time period, said first means further charging said second diffusion to said first voltage and grounding said first diffusion during a second time period, said second means further determining current flow through said transistors during said second time period.
Claim 13
Dependent Claim
90 words
A storage or transistor array according to claim 1-10, characterized by a field effect transistor having spaced apart diffusions (38, 40) interconnected by a channel, means for selectively increasing the threshold to channel conductivity of at least one of said diffusions, means (50, 52) for applying a voltage to one of said diffusions having a polarity and magnitude sufficient to neutralize said increased threshold to channel conductivity during a given time period, and means for sensing (51A, 51B) current flow between said spaced apart difiusions during said given time period.
References Cited (Backward Citations)
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