US4604732A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power supply dependent voltage reference circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1984-05-29
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Granted: 1986-08-05
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Expires: 2004-05-29
Abstract
Abstract A circuit adapted for use in comparing voltages in a manner that is insensitive to power supply variations includes a pair of reference cells controlling the reference voltage of a sense amplifier through control of a pair of reference transistors and an input circuit for conditioning data having a matched input pair of transistors, so that input data will control the voltage on the input terminal of a sense amplifier in a manner such that both inputs to the sense amp track voltage, thermal and processing variations.
Inventors
- 👤 Hiep Van Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C16/30; G11C2211/00; G11C2211/56; G11C2211/563; G11C2211/5634
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
226 words
A circuit for sensing a voltage state comprising: a conditioning circuit responsive to an applied input data voltage for generating a conditioned data voltage on a conditioned input node; a voltage reference circuit for generating a reference voltage on a reference node; and sensing means for comparing said conditioned data voltage and said reference voltage; in which said voltage reference circuit comprises means for supplying current to a reference node and first and second reference transistors connected in parallel between said reference node and a second node, each of which first and second reference transistors has a gate controlled by first and second dummy memory cells having predetermined stored data, whereby the voltage of said reference node and the impedance of said first and second reference transistors between said reference node and said second node is dependent on said stored data; in which said conditioning circuit comprises means for supplying current to a conditioned input node and a pair of corresponding first and second transistors, each of which is matched to one of said first and second reference transistors, which pair of corresponding transistors are connected in parallel between said conditioned input node and ground and both of which corresponding transistors have their gates connected to an input node, whereby an applied input data voltage produces a corresponding conditioned data voltage on said conditoned input node.
Claim 2
Dependent Claim
226 words
A circuit for sensing a voltage state comprising: a conditioning circuit responsive to an applied input data voltage for generating a conditioned data voltage on a conditioned input node; a voltage reference circuit for generating a reference voltage on a reference node; and sensing means for comparing said conditioned data voltage and said reference voltage; in which said voltage reference circuit comprises means for supplying current to a reference node and first and second reference transistors connected in parallel between said reference node and a second node, each of which first and second reference transistors has a gate controlled by first and second dummy memory cells having predetermined stored data, whereby the voltage of said reference node and the impedance of said first and second reference transistors between said reference node and said second node is dependent on said stored data; in which said conditioning circuit comprises means for supplying current to a conditioned input node and a pair of corresponding first and second transistors, each of which is matched to one of said first and second reference transistors, which pair of corresponding transistors are connected in parallel between said conditioned input node and ground and both of which corresponding transistors have their gates connected to an input node, whereby an applied input data voltage produces a corresponding conditioned data voltage on said conditoned input node.
Claim 3
Dependent Claim
50 words
A circuit according to claim 1, in which said means for supplying current to said reference node and said means for supplying current to said conditioned input node each comprises a current path, having a predetermined impedance, between a supply voltage node and said conditioned input node or reference node.
Claim 4
Dependent Claim
46 words
A circuit according to claim 1, in which said first and second dummy memory cells impose first and second predetermined voltages on first and second controlled gates, one of said predetermined voltages representing a logic one and the other of said voltages representing a logic zero.
Claim 5
Dependent Claim
39 words
A circuit according to claim 3, in which both of said predetermined voltages are above the threshold voltage of the corresponding one of said first and second transistors, whereby both of said first and second transistors are turned on.
Claim 6
Dependent Claim
36 words
A circuit according to claim 1, in which each of said first and second dummy memory cells imposes first and second predetermined voltages representative of two out of a set of at least three data states.
Claim 7
Dependent Claim
126 words
A circuit for sensing one of at least three possible voltage states comprising: at least one conditioning circuit responsive to an applied input data voltage for generating at least one conditioned data voltage on a conditioned node; at least two voltage reference circuits for generating at least two reference voltages on at least two reference nodes; and at least one sensing means for comparing said conditioned data voltage with said at least two reference voltages; in which a first comparison means compares said conditioned output voltage with one of said at least two reference voltages to produce a first comparison signal; and a second comparison means compares said conditioned output voltage with another of said at least two reference voltages to produce a second comparison signal.
Claim 8
Dependent Claim
126 words
A circuit for sensing one of at least three possible voltage states comprising: at least one conditioning circuit responsive to an applied input data voltage for generating at least one conditioned data voltage on a conditioned node; at least two voltage reference circuits for generating at least two reference voltages on at least two reference nodes; and at least one sensing means for comparing said conditioned data voltage with said at least two reference voltages; in which a first comparison means compares said conditioned output voltage with one of said at least two reference voltages to produce a first comparison signal; and a second comparison means compares said conditioned output voltage with another of said at least two reference voltages to produce a second comparison signal.
Claim 9
Dependent Claim
153 words
A circuit according to claim 6, in which a first one of said at least two voltage reference circuits comprises first and second parallel reference transistors controlled by first and second stored data voltages, said first and second parallel reference transistors comprising a current path having a predetermined impedance from a first one of said reference nodes to ground, thereby establishing a first reference voltage on said first reference node; and a second one of said at least two voltage reference circuits comprises third and fourth parallel reference transistors controlled by said second stored data voltage and a third stored data voltage respectively, said second stored data voltage being intermediate said first and third stored data voltages, said third and fourth parallel reference transistors comprising a current path having a predetermined impedance from a second one of said reference nodes to ground, thereby establishing a second reference voltage on said second reference node.
Claim 10
Dependent Claim
162 words
A circuit for sensing an input voltage comprising: an input side comprising a first pull-up transistor connected between a supply voltage node and a gate node and an input pair of transistors connected between said gate node and a bias node connected to ground, both of the gates of said input transistors being controlled by said input voltage, whereby the impedance of said input side between said supply voltage node and said bias node is affected by said input voltage; an output side comprising a second pull-up transistor connected between said supply voltage node and an output node, both pull-up transistors having their gates controlled by said gate node; and a pair of reference transistors connected in parallel between said output node and said bias node, said pair of reference transistors having their gates controlled by first and second reference cells storing first and second reference voltages, whereby said pair of reference transistors have a parallel impedance determined by said reference voltages.
Claim 11
Dependent Claim
162 words
A circuit for sensing an input voltage comprising: an input side comprising a first pull-up transistor connected between a supply voltage node and a gate node and an input pair of transistors connected between said gate node and a bias node connected to ground, both of the gates of said input transistors being controlled by said input voltage, whereby the impedance of said input side between said supply voltage node and said bias node is affected by said input voltage; an output side comprising a second pull-up transistor connected between said supply voltage node and an output node, both pull-up transistors having their gates controlled by said gate node; and a pair of reference transistors connected in parallel between said output node and said bias node, said pair of reference transistors having their gates controlled by first and second reference cells storing first and second reference voltages, whereby said pair of reference transistors have a parallel impedance determined by said reference voltages.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |