Method and circuitry for storing discrete amounts of charge in a single memory element

Claim 2

In a memory array including a memory cell, a method of programming the memory cell to a selected state representing a pattern of data bits, the method comprising the steps of: a) applying a programming pulse to the memory array, the programming pulse having a programming voltage level; b) generating a verify signal by determining whether the memory cell has been programmed to the selected state; c) increasing the programming voltage level if the verify signal indicates that the memory cell has not been programmed to the selected state; and d) repeating steps a) through c) until the verify signal indicates that the memory cell has been programmed to the selected state.

Claim 3

The method of claim 1, wherein the programming pulse has a program pulse duration having an initial value in step a) and wherein step c) further comprises setting the program pulse duration to a second value that is less than the initial value.

Claim 4

The method of claim 2 wherein the initial value of the program pulse duration is sufficient to cause programming of the memory cell to occur in a saturated region.

Claim 5

The method of claim 2, wherein the memory cell includes a bitline and the programming pulse includes a bitline voltage coupled to the bitline.

Claim 6

The method of claim 4, further comprising the step of: e) trimming the bitline voltage such that the initial duration of the programming pulse in step a) causes the memory cell to program in a saturated region.

Claim 7

The method of claim 1, wherein the selected state represents a pattern of two bits.

Claim 8

The method of claim 1, wherein the selected state represents a pattern of three bits.

Claim 9

The method of claim 1, wherein the selected state represents a pattern of 3.5 bits.

Claim 10

The method of claim 1, wherein the selected state represents a pattern of four bits.

Claim 11

The method of claim 1, wherein the selected state represents a noninteger number of bits.

Claim 12

The method of claim 1, wherein the selected state is represented by a range of threshold voltages.

Claim 13

The method of claim 1, wherein the selected state is represented by a range of drain currents.

Claim 14

The method of claim 1, wherein the selected state is represented by an amount of charge.

Claim 15

In a memory array including a first memory cell and a second memory cell, a method of programming the first memory cell to a first state and programming the second memory cell to a second state, the first state representing a first pattern of a multiplicity of bits and the second state representing a second pattern of the multiplicity of bits, the method comprising the steps of: a) applying a programming pulse to the memory array, the programming pulse having a programming voltage level; b) generating a first verify signal indicative of whether the first memory cell has been programmed to the first state; c) generating a second verify signal indicative of whether the second memory cell has been programmed to the second state; d) increasing the programming voltage level if the first verify signal indicates that the first memory cell has not been programmed to the first state or the second verify signal indicates that the second memory cell has not been programmed to the second state; e) inhibiting further programming of the first memory cell if the first verify signal indicates that first memory cell has been programmed to the first state; f) inhibiting further programming of the second memory cell if the second verify signal indicates that second memory cell has been programmed to the second state; and g) repeating steps a) through f) until the first verify signal indicates that the first memory cell has been programmed to the first state and the second verify signal indicates that the second memory cell has been programmed to the second state.

Claim 16

In a memory array including a first memory cell and a second memory cell, a method of programming the first memory cell to a first state and programming the second memory cell to a second state, the first state representing a first pattern of a multiplicity of bits and the second state representing a second pattern of the multiplicity of bits, the method comprising the steps of: a) applying a programming pulse to the memory array, the programming pulse having a programming voltage level; b) generating a first verify signal indicative of whether the first memory cell has been programmed to the first state; c) generating a second verify signal indicative of whether the second memory cell has been programmed to the second state; d) increasing the programming voltage level if the first verify signal indicates that the first memory cell has not been programmed to the first state or the second verify signal indicates that the second memory cell has not been programmed to the second state; e) inhibiting further programming of the first memory cell if the first verify signal indicates that first memory cell has been programmed to the first state; f) inhibiting further programming of the second memory cell if the second verify signal indicates that second memory cell has been programmed to the second state; and g) repeating steps a) through f) until the first verify signal indicates that the first memory cell has been programmed to the first state and the second verify signal indicates that the second memory cell has been programmed to the second state.

Claim 17

The method of claim 14, wherein the multiplicity of bits equals two.

Claim 18

The method of claim 14, wherein the multiplicity of bits equals four.

Claim 19

The method of claim 14, wherein the multiplicity of bits equals three.

Claim 20

The method of claim 14, wherein the multiplicity of bits equals 3.5.

Claim 21

The method of claim 14, wherein the multiplicity of bits is equal to a noninteger number.

Claim 22

The method of claim 14, wherein the first memory cell is volatile.

Claim 23

The method of claim 14, wherein the first memory cell is nonvolatile.

Claim 24

The method of claim 14, wherein the first and second states are each represented by a range of threshold voltages.

Claim 25

The method of claim 14, wherein the first state and the second state are each represented by a range of drain currents.

Claim 26

The method of claim 14, wherein the first state and the second state are each represented by an amount of charge.

Claim 27

The method of claim 14, wherein the memory array includes a first bitline coupled to the first memory cell, a second bitline coupled to the second memory cell, and a wordline coupled to the first memory cell and the second memory cell.

Claim 28

The method of claim 25, wherein step a) includes coupling the programming voltage to the wordline and a second voltage to the first bitline and a third voltage to the second bitline.

Claim 29

The method of claim 25, wherein the second voltage and third voltage are below an impact ionization bipolar turn on voltage.

Claim 30

The method of claim 25, wherein the programming pulse has a duration, the method further comprising the steps of: h) trimming the second voltage and the third voltage such that programming of the first memory cell and the second memory cell occurs in a saturated region.

Claim 31

The method of claim 25, wherein step e) comprises coupling the first bitline to a fourth voltage during application of programming pulses to the memory array.

Claim 32

The method of claim 29, wherein the fourth voltage is ground.

Claim 33

The method of claim 14, wherein the programming voltage level ranges from a minimum of approximately 6 volts to a maximum of approximately 12 volts.

Claim 34

In a memory array including a first memory cell and a second memory cell, a method of programming the first memory cell to a first state and programming the second memory cell to a second state, the first state representing a first pattern of a multiplicity of bits and the second state representing a second pattern of the multiplicity of bits, the method comprising the steps of: a) applying a programming pulse to the memory array, the programming pulse having a program voltage level and a duration, the duration having an initial value; b) generating a first verify signal indicative of whether the first memory cell has been programmed to the first state; c) generating a second verify signal indicative of whether the second memory cell has been programmed to the second state; d) increasing the program voltage level of the programming pulse by a step size and setting the duration to a subsequent value that is less than the initial value if the first verify signal indicates that the first memory cell has not been programmed to the first state or if the second verify signal indicates that the second memory cell has not been programmed to the second state; e) inhibiting further programming of the first memory cell if the first verify signal indicates that first memory cell has been programmed to the first state; f) inhibiting further programming of the second memory cell if the second verify signal indicates that second memory cell has been programmed to the second state; and g) repeating steps a) through f) until the first verify signal indicates that the first memory cell has been programmed to the first state and the second verify signal indicates that the second memory cell has been programmed to the second state.

Claim 35

In a memory array including a first memory cell and a second memory cell, a method of programming the first memory cell to a first state and programming the second memory cell to a second state, the first state representing a first pattern of a multiplicity of bits and the second state representing a second pattern of the multiplicity of bits, the method comprising the steps of: a) applying a programming pulse to the memory array, the programming pulse having a program voltage level and a duration, the duration having an initial value; b) generating a first verify signal indicative of whether the first memory cell has been programmed to the first state; c) generating a second verify signal indicative of whether the second memory cell has been programmed to the second state; d) increasing the program voltage level of the programming pulse by a step size and setting the duration to a subsequent value that is less than the initial value if the first verify signal indicates that the first memory cell has not been programmed to the first state or if the second verify signal indicates that the second memory cell has not been programmed to the second state; e) inhibiting further programming of the first memory cell if the first verify signal indicates that first memory cell has been programmed to the first state; f) inhibiting further programming of the second memory cell if the second verify signal indicates that second memory cell has been programmed to the second state; and g) repeating steps a) through f) until the first verify signal indicates that the first memory cell has been programmed to the first state and the second verify signal indicates that the second memory cell has been programmed to the second state.

Claim 36

The method of claim 31, wherein each of the first state and the second state is represented by a range of threshold voltages.

Claim 37

The method of claim 32, wherein each of the first state and the second state is represented by a range of drain currents.

Claim 38

The method of claim 32, wherein each of the first state and the second state is represented by an amount of charge.

Claim 39

The method of claim 32, wherein the memory array is volatile.

Claim 40

The method of claim 32, wherein the memory array is nonvolatile.

Claim 41

The method of claim 32, wherein the multiplicity of bits equals three.

Claim 42

The method of claim 32, wherein the multiplicity of bits equals 3.5.

Claim 43

The method of claim 32, wherein the multiplicity of bits equals two.

Claim 44

The method of claim 32, wherein the multiplicity of bits equals four.

Claim 45

The method of claim 32, wherein the multiplicity of bits equals a noninteger number.

Claim 46

The method of claim 32, wherein the memory array includes a first bitline coupled to the first memory cell, a second bitline coupled to the second memory cell and a wordline coupled to the first memory cell and the second memory cell.

Claim 47

The method of claim 32, wherein step a) includes coupling the programming voltage to the wordline, a second voltage to the first bitline and a third voltage to the second bitline.

Claim 48

The method of claim 44 wherein the second voltage and third voltage are below an impact ionization bipolar turn on voltage.

Claim 49

The method of claim 45, wherein the second voltage is less than 6.6 volts.

Claim 50

The method of claim 45, wherein the second voltage is greater than 5.1 volts.

Claim 51

The method of claim 44, wherein the third voltage is less than 6.6 volts.

Claim 52

The method of claim 48 wherein the third voltage is greater than 5.1 volts.

Claim 53

The method of claim 44, wherein step e) comprises setting the second voltage equal to a fourth voltage.

Claim 54

The method of claim 50, wherein the fourth voltage is ground.

Claim 55

The method of claim 44, wherein step f) comprises setting the third voltage equal to a fifth voltage.

Claim 56

The method of claim 52, wherein the fifth voltage is ground.

Claim 57

The method of claim 32, wherein the programming voltage level ranges from a minimum of approximately 6 volts to a maximum of approximately 12 volts.

Claim 58

The method of claim 32, wherein the step size is between 0.1 volts and 0.5 volts.

Claim 59

The method of claim 32, wherein the duration is sufficient to program in a saturated region of the first memory cell and the second memory cell.