Memory device employing multilevel storage circuits

Claim 2

A memory device, comprising: m×n (where m≧1, n≧1, and m and n are integers) memory cells M 11 to M 1n , M 21 to M 2n , . . . , and M m1 to M mn ; m data lines A 1 to A m operatively connected to corresponding memory cells; m column select lines B 1 to B m providing a column select signal;

Claim 3

n word lines C 1 to C n operatively connected to corresponding memory cells and providing a word select signal; write means for providing on data line A i q-level information corresponding to binary data of plural bits when selected by the column select signal; readout means for simultaneously outputting binary data of plural bits corresponding to the q-level information provided from the memory cell M ij (where j=1, 2, . . . n) on the data line A i when selected by the column select signal, said readout means comprising m multilevel detectors J 1 to J m connected to corresponding data lines, m gate circuits L 1 to L m connected to corresponding multilevel detectors and m encoders Q 1 to Q m connected between corresponding column select lines and gate circuits, and the multilevel detector J i including (q-1) comparators, each having one signal input terminal and one reference input terminal, and where the signal input terminal of the (q-1) comparators are connected in common to the data line A i to which the selected memory cell M ij is connected and the reference input terminals of the (q-1) comparators are supplied with (q-1) different reference levels, respectively, the memory cell M ij , when selected by the word select signal from the word line C j , storing the q-level information provided on the data line A i and when the gate circuit L i is selected by the column select signal from the column select line B i , the multilevel detector J i provides via the selected gate circuit L i to the encoder Q i , a sense circuit output corresponding to the q-level information in the memory cell M ij and the encoder Q i outputs binary data of plural bits representing the q-level information.

Claim 4

n word lines C 1 to C n operatively connected to corresponding memory cells and providing a word select signal; write means for providing on data line A i q-level information corresponding to binary data of plural bits when selected by the column select signal; readout means for simultaneously outputting binary data of plural bits corresponding to the q-level information provided from the memory cell M ij (where j=1, 2, . . . n) on the data line A i when selected by the column select signal, said readout means comprising m multilevel detectors J 1 to J m connected to corresponding data lines, m gate circuits L 1 to L m connected to corresponding multilevel detectors and m encoders Q 1 to Q m connected between corresponding column select lines and gate circuits, and the multilevel detector J i including (q-1) comparators, each having one signal input terminal and one reference input terminal, and where the signal input terminal of the (q-1) comparators are connected in common to the data line A i to which the selected memory cell M ij is connected and the reference input terminals of the (q-1) comparators are supplied with (q-1) different reference levels, respectively, the memory cell M ij , when selected by the word select signal from the word line C j , storing the q-level information provided on the data line A i and when the gate circuit L i is selected by the column select signal from the column select line B i , the multilevel detector J i provides via the selected gate circuit L i to the encoder Q i , a sense circuit output corresponding to the q-level information in the memory cell M ij and the encoder Q i outputs binary data of plural bits representing the q-level information.

Claim 5

A memory device according to claim 1, wherein said write means comprises m write circuits D 1 to D m connected to corresponding column select lines and m gate circuits I 1 to I m connected between corresponding data lines and write circuits, and when the gate circuit I i is selected by the column select signal from the column select line B i , the write circuit D i outputs the q-level information corresponding to the binary data of plural bits on the data line A i via the selected gate circuit I i .

Claim 6

A memory device according to claim 1, wherein said write means comprises a write circuit connected to the column select lines and common to the data lines A 1 to A m and m gate circuits I 1 to I m connected between the write circuit and corresponding data lines, and when the gate circuit I i is selected by the column select signal from the column select line B i , the write circuit outputs the q-level information corresponding to the binary data of plural bits on the data line A i via the selected gate circuit I i .

Claim 7

A memory device according to claim 1, wherein said write means comprises m write circuits D 1 to D m connected to corresponding column select lines and m gate circuits I 1 to I m connected between corresponding write circuits and data lines, and when the gate circuit I i is selected by the column select signal from the column select line B i , the write circuit D i provides, via the selected gate circuit I i on the data line A i , the q-level information corresponding to the binary data of plural bits.

Claim 8

A memory device according to claim 1, further comprising m refresh circuits E 1 to E m connected to corresponding data lines, multilevel detector circuits and gate circuits, the refresh circuit E i provides q-level information corresponding to the sense circuit output signal from the multilevel detector J i on the data line A i for rewrite into the memory cell M ij .

Claim 9

A memory device according to claim 4, further comprising m refresh circuits E 1 to E m , connected to corresponding data lines, multilevel detector circuits and gate circuits, the refresh circuit E i provides q-level information corresponding to the sense circuit output signal from the multilevel detector J i on the data line A i for rewrite into the memory cell M ij .

Claim 10

A memory device according to claim 1, wherein said write means comprises a write circuit connected to the column select lines and common to the data lines A 1 and A m gate circuits I 1 to I m connected between the write circuit and corresponding data lines, and when the gate circuit I i is selected by the column select signal from the column select line B i , the write circuit provides the q-level information corresponding to the binary data of plural bits on the data line A i via the selected gate circuit I i .

Claim 11

A memory device according to claim 1, further comprising m refresh circuits E 1 to E m connected to corresponding data lines, multilevel detectors and gate circuits, the refresh circuit E i provides q-level information corresponding to the sense circuit output signal from the multilevel detector J i on the data line A i for rewrite into the memory cell M ij .

Claim 12

A memory device according to claim 9, further comprising m refresh circuits E 1 to E m connected to corresponding data lines, the refresh circuit E i provides q-level information corresponding to the sense circuit output signal from the multilevel detector J i on the data line A i for rewrite into the memory cell M ij .

Claim 13

A memory device according to claim 1, wherein the comparators each comprise: a first MOS transistor having a drain connected to a first node and having a gate; a second MOS transistor of the same conductivity type as the first MOS transistor, having a gate connected to the first node and having a drain; a first capacitance connected between the first node and ground; a third MOS transistor different in conductivity type from the first MOS transistor, having a source connected to the drain of the first MOS transistor and having a gate, the gate of the first MOS transistor and the drain of the second MOS transistor being connected to a second node; a second capacitance connected between the second node and ground; and a fourth MOS transistor different in conductivity from the second MOS transistor, having a source connected to the drain of the second MOS transistor and having a gate, and two input signals the potential difference of which is to be detected are applied to the gates of the third and fourth MOS transistors and then charges stored in the first and second capacitances are discharged via the first and second MOS transistors.

Claim 14

A memory device according to claims 1, 5, 6, 8 or 9, further comprising: a selector, connected between said data lines and said multilevel detectors, for selectively connecting the data lines to the multilevel detectors; dummy cells each connected to a corresponding data line and selected by the word select signals from the word lines, the number of the data lines being 2(q-1)×l (where l≧1) and the data lines are divided into l groups, each comprising (q-1) pairs of two different data lines; and l sense circuits corresponding to the l groups of data lines, where each sense circuit comprises (q-1) multilevel detectors, each including (q-1) comparators each having one signal input terminal connected to a corresponding data line and one reference input terminal, and the selector selects one of the data lines of each data line pair for connection to the signal input terminals of all the comparators of the corresponding multilevel detector of the corresponding sense circuit and selects the other of the data lines of each data line pair for connection to the reference input terminals of all the comparators each of which belongs to different multilevel detectors of the corresponding sense circuits, the other (q-1) data lines having connected thereto (q-1) different dummy cells providing different reference levels, respectively.

Claim 15

A memory device according to claim 11, wherein the comparators each comprise: a first MOS transistor having a drain connected to a first node and having a gate; a second MOS transistor of the same conductivity type as the first MOS transistor, having a gate connected to the first node and having a drain; a first capacitance connected between the first node and ground; a third MOS transistor different in conductivity type from the first MOS transistor, having a source connected to the drain of the first MOS transistor and having a gate, the gate of the first MOS transistor and the drain of the second MOS transistor being connected to a second node; a second capacitance connected between the second node and ground; a fourth MOS transistor different in conductivity from the second MOS transistor, having a source connected to the drain of the second MOS transistor and having a gate, and two input signals the potential difference of which is to be detected are applied to the gates of the third and fourth MOS transistors and then charges stored in the first and second capacitances are discharged via the first and second MOS transistors.

Claim 16

A memory device provided with data lines having connected thereto integrated memory cells, capable of q (where q≧3) different information storage states, and word lines for selecting the memory cells, said device comprising: a row decoder connected to the word lines and including a word driver for selecting the memory cells connected to a specified one of the word lines; a selector, connected to the memory cells, for selecting a specified one of the data lines; at least (q-1) 2 comparators connected to the selector and for connection to the selected data lines; and at least (q-1) different dummy cells, connected to the selector, for generating reference levels in the data lines; and the comparators each have one signal input terminal and one reference input terminal, the (q-1) comparators forming a multilevel detector and (q-1) multilevel detectors forming a sense circuit having (q-1) common signal input terminals for connecting together the signal input terminals of the (q-1) comparators of each multilevel detector and (q-1) common reference input terminals for connecting together the reference input terminals of the (q-1) comparators each of which belong to different multilevel detector, where more than (q-1) memory cells and the (q-1) different dummy cells are selected simultaneously under control of the row decoder including the word driver, the selected memory cells and the dummy cells are connected to 2(q-1) different data lines, (q-1) of the data lines to which the selected memory cells are connected are connected to different common signal input terminals under the control of the selector, and the (q-1) data lines to which the selected (q-1) different dummy cells are connected are connected to different common reference input terminals.

Claim 17

A memory device provided with data lines having connected thereto integrated memory cells, capable of q (where q≧3) different information storage states, and word lines for selecting the memory cells, said device comprising: a row decoder connected to the word lines and including a word driver for selecting the memory cells connected to a specified one of the word lines; a selector, connected to the memory cells, for selecting a specified one of the data lines; at least (q-1) 2 comparators connected to the selector and for connection to the selected data lines; and at least (q-1) different dummy cells, connected to the selector, for generating reference levels in the data lines; and the comparators each have one signal input terminal and one reference input terminal, the (q-1) comparators forming a multilevel detector and (q-1) multilevel detectors forming a sense circuit having (q-1) common signal input terminals for connecting together the signal input terminals of the (q-1) comparators of each multilevel detector and (q-1) common reference input terminals for connecting together the reference input terminals of the (q-1) comparators each of which belong to different multilevel detector, where more than (q-1) memory cells and the (q-1) different dummy cells are selected simultaneously under control of the row decoder including the word driver, the selected memory cells and the dummy cells are connected to 2(q-1) different data lines, (q-1) of the data lines to which the selected memory cells are connected are connected to different common signal input terminals under the control of the selector, and the (q-1) data lines to which the selected (q-1) different dummy cells are connected are connected to different common reference input terminals.