US4122541A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory device
Assignee: Toshiba Corp
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Filing: 1976-08-25
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Granted: 1978-10-24
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Expires: 1996-08-25
Abstract
Abstract A memory apparatus comprises a plurality of memory cells each having a bistable circuit comprising a pair of field effect transistors, a pair of switching transistors connected between a power supply and each output terminal of said paired field effect transistors, and a plurality of pairs of variable threshold insulated gate field effect transistors connected in parallel with the pair of switching transistors, the variable threshold insulated gate field effect transistors in pair constituting a non-volatile memory cell element, and a plurality of gate control lines connected in common to the gates of the paired variable threshold insulated gate field effect transistors.
Inventors
- 👤 Yukimasa Uchida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:46
CPC Classifications
G; G11; G11C; G11C14/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
283 words
A nonvolatile memory device comprising: an array of nonvolatile memory cells each including a bistable circuit including a power supply terminal, a pair of output terminals, a pair of resistive means connected at one end to said power supply terminal, a pair of driven field effect transistors whose drains are connected to said pair of output terminals, respectively to perform a flip-flop function, and first and second switching field effect transistors respectively connected between said pair of output terminals and said pair of corresponding resistive means; a plurality of first variable threshold field effect transistors each connected in parallel with said first switching field effect transistors; and a plurality of second variable threshold field effect transistors each connected in parallel with said second switching field effect transistors, said plurality of second variable threshold field effect transistors being the same in number as said plurality of first variable threshold field effect transistors; a pair of transfer field effect transistors respectively connected at drains to sid output terminals; a plurality of word lines each connected to the gate of said pair of transfer field effect transistors in each row; a plurality of paired digit lines each pair of which are connected to the respective sources of said pair of transfer field effect transistors in each column; and a plurality of control lines provided in the same number as said plurality of first variable threshold field effect transistors and each connected to the gate of one of said plurality of first variable threshold field effect transistors in each of said nonvolatile memory cells and to the gate of one of said plurality of second variable threshold field effect transistors in each of said nonvolatile memory cells.
Claim 2
Dependent Claim
283 words
A nonvolatile memory device comprising: an array of nonvolatile memory cells each including a bistable circuit including a power supply terminal, a pair of output terminals, a pair of resistive means connected at one end to said power supply terminal, a pair of driven field effect transistors whose drains are connected to said pair of output terminals, respectively to perform a flip-flop function, and first and second switching field effect transistors respectively connected between said pair of output terminals and said pair of corresponding resistive means; a plurality of first variable threshold field effect transistors each connected in parallel with said first switching field effect transistors; and a plurality of second variable threshold field effect transistors each connected in parallel with said second switching field effect transistors, said plurality of second variable threshold field effect transistors being the same in number as said plurality of first variable threshold field effect transistors; a pair of transfer field effect transistors respectively connected at drains to sid output terminals; a plurality of word lines each connected to the gate of said pair of transfer field effect transistors in each row; a plurality of paired digit lines each pair of which are connected to the respective sources of said pair of transfer field effect transistors in each column; and a plurality of control lines provided in the same number as said plurality of first variable threshold field effect transistors and each connected to the gate of one of said plurality of first variable threshold field effect transistors in each of said nonvolatile memory cells and to the gate of one of said plurality of second variable threshold field effect transistors in each of said nonvolatile memory cells.
Claim 3
Dependent Claim
28 words
A nonvolatile memory device according to claim 1 in which said memory cell further includes a field effect transistor connected between the output terminals of said bistable circuit.
Claim 4
Dependent Claim
214 words
A nonvolatile memory cell comprising: a bistable circuit including a power supply terminal, a pair of output terminals, a pair of resistive means connected at one end to said power supply terminal, a pair of driver field effect transistors whose drains are connected to said pair of output terminals, respectively to perform a flip-flop function, and first and second switching field effect transistors respectively connected between said pair of output terminals and said pair of corresponding resistive means; a plurality of first variable threshold field effect transistors each connected in parallel with said first switching field effect transistors; a plurality of second variable threshold field effect transistors each connected in parallel with said second switching field effect transistors, said plurality of second variable threshold field effect transistors being the same in number as said plurality of first variable threshold field effect transistors; a plurality of control lines provided in the same number as said plurality of first variable threshold field effect transistors and each connected to the gate of one of said plurality of first variable threshold field effect transistors and to the gate of corresponding one of said plurality of second variable threshold field effect transistors; and a pair of transfer field effect transistors respectively connected at one terminal to said output terminals.
Claim 5
Dependent Claim
214 words
A nonvolatile memory cell comprising: a bistable circuit including a power supply terminal, a pair of output terminals, a pair of resistive means connected at one end to said power supply terminal, a pair of driver field effect transistors whose drains are connected to said pair of output terminals, respectively to perform a flip-flop function, and first and second switching field effect transistors respectively connected between said pair of output terminals and said pair of corresponding resistive means; a plurality of first variable threshold field effect transistors each connected in parallel with said first switching field effect transistors; a plurality of second variable threshold field effect transistors each connected in parallel with said second switching field effect transistors, said plurality of second variable threshold field effect transistors being the same in number as said plurality of first variable threshold field effect transistors; a plurality of control lines provided in the same number as said plurality of first variable threshold field effect transistors and each connected to the gate of one of said plurality of first variable threshold field effect transistors and to the gate of corresponding one of said plurality of second variable threshold field effect transistors; and a pair of transfer field effect transistors respectively connected at one terminal to said output terminals.
Claim 6
Dependent Claim
28 words
A nonvolatile memory cell according to claim 3, in which said memory cell further includes a field effect transistor connected between the output terminals of said bistable circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-23 | 1982-04-24 | 1982-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-23 | 1986-04-24 | 1986-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-23 | 1990-04-24 | 1990-10-24 | $7700.00 | Window Closed / Lapsed |