US6104640A
Expired / Lapsed
US
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Electrically alterable non-violatile memory with N-bits per cell
Assignee: MLC Intellectual Property LLC
•
Filing: 1998-11-18
•
Granted: 2000-08-15
•
Expires: 2018-11-18
Abstract
Abstract An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signal which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.
Inventors
- 👤 Gerald J. Banks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:33
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C16/14; G11C16/16; G11C16/32; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634; G11C2211/564; G11C2211/5642; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
93 words
A method of programming an electrically alterable non-volatile memory cell having more than two memory states, comprising: applying a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal and a subsequent programming signal which have different characteristics, said first programming signal programming said memory cell by a first increment and said subsequent programming signal programming said memory cell by a second increment smaller than said first increment.
Claim 2
Independent Claim
93 words
A method of programming an electrically alterable non-volatile memory cell having more than two memory states, comprising: applying a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal and a subsequent programming signal which have different characteristics, said first programming signal programming said memory cell by a first increment and said subsequent programming signal programming said memory cell by a second increment smaller than said first increment.
Claim 3
Dependent Claim
33 words
A method according to claim 1, wherein at least said first programming signal and said subsequent programming signal are applied to said memory cell before said memory cell reaches the selected memory state.
Claim 4
Dependent Claim
32 words
A method according to claim 1, wherein each programming signal of said plurality subsequent to said first programming signal programs said memory cell by a respective increment smaller than said first increment.
Claim 5
Dependent Claim
20 words
A method according to claim 1, wherein the plurality of programming signals program said memory cell in successively decreasing increments.
Claim 6
Dependent Claim
22 words
A method according to claim 1, wherein said memory cell is a floating gate memory cell constructed with a single floating gate.
Claim 7
Dependent Claim
29 words
A method according to claim 1, wherein said memory cell is a floating gate FET, and said plurality of programming signals are applied to a drain of said FET.
Claim 8
Dependent Claim
101 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming signal generating device which applies a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal and a subsequent programming signal which have different characteristics, said first programming signal programming said memory cell by a first increment and said subsequent programming signal programming said memory cell by a second increment smaller than said first increment.
Claim 9
Dependent Claim
101 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming signal generating device which applies a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal and a subsequent programming signal which have different characteristics, said first programming signal programming said memory cell by a first increment and said subsequent programming signal programming said memory cell by a second increment smaller than said first increment.
Claim 10
Dependent Claim
33 words
An apparatus according to claim 7, wherein at least said first programming signal and said subsequent programming signal are applied to said memory cell before said memory cell reaches the selected memory state.
Claim 11
Dependent Claim
32 words
An apparatus according to claim 7, wherein each programming signal of said plurality subsequent to said first programming signal programs said memory cell by a respective increment smaller than said first increment.
Claim 12
Dependent Claim
20 words
An apparatus according to claim 7, wherein the plurality of programming signals program said memory cell in successively decreasing increments.
Claim 13
Dependent Claim
22 words
An apparatus according to claim 7, wherein said memory cell is a floating gate memory cell constructed with a single floating gate.
Claim 14
Dependent Claim
29 words
An apparatus according to claim 7, wherein said memory cell is a floating gate FET, and said plurality of programming signals are applied to a drain of said FET.
Claim 15
Independent Claim
91 words
A method of programming an electrically alterable non-volatile memory cell having more than two selectable memory states, comprising: for each of said memory states, when selected, applying a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, said plurality of programming signals including at least a first programming signal which programs said memory cell by a first increment and a subsequent programming signal which programs said memory cell by a second increment smaller than said first increment.
Claim 16
Independent Claim
91 words
A method of programming an electrically alterable non-volatile memory cell having more than two selectable memory states, comprising: for each of said memory states, when selected, applying a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, said plurality of programming signals including at least a first programming signal which programs said memory cell by a first increment and a subsequent programming signal which programs said memory cell by a second increment smaller than said first increment.
Claim 17
Dependent Claim
33 words
A method according to claim 13, wherein at least said first programming signal and said subsequent programming signal are applied to said memory cell before said memory cell reaches the selected memory state.
Claim 18
Dependent Claim
32 words
A method according to claim 13, wherein each programming signal of said plurality subsequent to said first programming signal programs said memory cell by a respective increment smaller than said first increment.
Claim 19
Dependent Claim
20 words
A method according to claim 13, wherein the plurality of programming signals program said memory cell in successively decreasing increments.
Claim 20
Dependent Claim
22 words
A method according to claim 13, wherein said memory cell is a floating gate memory cell constructed with a single floating gate.
Claim 21
Dependent Claim
29 words
A method according to claim 13, wherein said memory cell is a floating gate FET, and said plurality of programming signals are applied to a drain of said FET.
Claim 22
Dependent Claim
21 words
A method according to claim 13, wherein said more than two memory states constitute all memory states of said memory cell.
Claim 23
Dependent Claim
101 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two selectable memory states; and a programming signal generating device which, for each of said memory states, when selected, operates to apply a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal which programs said memory cell by a first increment and a subsequent programming signal which programs said memory cell by a second increment smaller than said first increment.
Claim 24
Dependent Claim
101 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two selectable memory states; and a programming signal generating device which, for each of said memory states, when selected, operates to apply a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal which programs said memory cell by a first increment and a subsequent programming signal which programs said memory cell by a second increment smaller than said first increment.
Claim 25
Dependent Claim
33 words
An apparatus according to claim 20, wherein at least said first programming signal and said subsequent programming signal are applied to said memory cell before said memory cell reaches the selected memory state.
Claim 26
Dependent Claim
32 words
An apparatus according to claim 20, wherein each programming signal of said plurality subsequent to said first programming signal programs said memory cell by a respective increment smaller than said first increment.
Claim 27
Dependent Claim
20 words
An apparatus according to claim 20, wherein the plurality of programming signals program said memory cell in successively decreasing increments.
Claim 28
Dependent Claim
22 words
An apparatus according to claim 20, wherein said memory cell is a floating gate memory cell constructed with a single floating gate.
Claim 29
Dependent Claim
29 words
An apparatus according to claim 20, wherein said memory cell is a floating gate FET, and said plurality of programming signals are applied to a drain of said FET.
Claim 30
Dependent Claim
21 words
An apparatus according to claim 20, wherein said more than two memory states constitute all memory states of said memory cell.
Claim 31
Independent Claim
82 words
A method of programming an electrically alterable non-volatile memory cell having more than two memory states, comprising: applying a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal which programs said memory cell by a first increment and a subsequent programming signal which programs said memory cell by a second increment smaller than said first increment.
Claim 32
Independent Claim
82 words
A method of programming an electrically alterable non-volatile memory cell having more than two memory states, comprising: applying a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal which programs said memory cell by a first increment and a subsequent programming signal which programs said memory cell by a second increment smaller than said first increment.
Claim 33
Dependent Claim
20 words
A method according to claim 27, wherein the plurality of programming signals program said memory cell in successively decreasing increments.
Claim 34
Dependent Claim
33 words
A method according to claim 27, wherein at least said first programming signal and said subsequent programming signal are applied to said memory cell before said memory cell reaches the selected memory state.
Claim 35
Dependent Claim
32 words
A method according to claim 27, wherein each programming signal of said plurality subsequent to said first programming signal programs said memory cell by a respective increment smaller than said first increment.
Claim 36
Dependent Claim
22 words
A method according to claim 27, wherein said memory cell is a floating gate memory cell constructed with a single floating gate.
Claim 37
Dependent Claim
29 words
A method according to claim 27, wherein said memory cell is a floating gate FET, and said plurality of programming signals are applied to a drain of said FET.
Claim 38
Dependent Claim
90 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming signal generating device which applies a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal which programs said memory cell by a first increment and a subsequent programming signal which programs said memory cell by a second increment smaller than said first increment.
Claim 39
Dependent Claim
90 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming signal generating device which applies a plurality of programming signals to said memory cell so as to program said memory cell to a selected one of said memory states, the plurality of programming signals including at least a first programming signal which programs said memory cell by a first increment and a subsequent programming signal which programs said memory cell by a second increment smaller than said first increment.
Claim 40
Dependent Claim
19 words
An apparatus according to claim 33, wherein the plurality programming signals program said memory cell in successively decreasing increments.
Claim 41
Dependent Claim
33 words
An apparatus according to claim 33, wherein at least said first programming signal and said subsequent programming signal are applied to said memory cell before said memory cell reaches the selected memory state.
Claim 42
Dependent Claim
32 words
An apparatus according to claim 33, wherein each programming signal of said plurality subsequent to said first programming signal programs said memory cell by a respective increment smaller than said first increment.
Claim 43
Dependent Claim
22 words
An apparatus according to claim 33, wherein said memory cell is a floating gate memory cell constructed with a single floating gate.
Claim 44
Dependent Claim
29 words
An apparatus according to claim 33, wherein said memory cell is a floating gate FET, and said plurality of programming signals are applied to a drain of said FET.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-15 | 2004-02-14 | 2004-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-15 | 2008-02-14 | 2008-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-15 | 2012-02-14 | 2012-08-15 | $7700.00 | Window Closed / Lapsed |