US4558241A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier
Assignee: Fujitsu Ltd
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Filing: 1984-07-02
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Granted: 1985-12-10
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Expires: 2004-07-02
Abstract
Abstract A flip-flop type sense amplifier for a semiconductor memory device is disclosed, the sense amplifier comprising a pair of CMOS inverters cross-coupled with each other to form a CMOS flip-flop circuit having a pair of buffer circuits, for receiving the read-out voltage signals from multi-level memory cells and a predetermined reference voltage, respectively, and a pair of switching circuits for inverting a power source voltage across the flip-flop circuit through common sources of the flip-flop circuit, in response to the transition between a stand-by sequence and a latching operating. The common source of the p-channel transistors of the CMOS flip-flop circuit is connected to a negative potential source, and the common source of the n-channel transistors is connected to a positive potential source during a stand-by sequence, and vice versa, during a latching operation. This unique potential supply method enhances operational speed of the sense amplifier. In a multi-level memory device, a plurality of the sense amplifiers are connected in parallel for the discrimination of the read-out signals changing in a range of a few volts.
Inventors
- 👤 Yasuo Suzuki
- 👤 Hiroshi Hirao
- 👤 Yasuaki Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:42
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
281 words
A sense amplifier comprising: a flip-flop circuit including two n-channel MOS transistors having a common source and two p-channel MOS transistors having a common source; said n-channel transistors and said p-channel transistors forming pairs, each pair having a conduction channel connected in series and having a common gate connected to the node of the opposite pair of said n-channel transistor and said p-channel transistor; a first switching circuit for switching the polarity of the potential supplied to said common source of said n-channel transistors of said flip-flop circuit; a second switching circuit for switching the polarity of the potential supplied to said common source of said p-channel transistors of said flip-flop circuit; wherein the polarity of the potential at the common sources is inverted in response to the transition between a stand-by sequence and a latching operation; a first buffer circuit including a pair of n-channel MOS transistors having conduction channels connected in series between a positive potential source and a negative potential source, the gate of one of said transistors receiving read-out voltage signals from memory cells and the gate of the other of said transistors being connected to the positive potential source, said transistors having a junction connected to a first of said nodes of said flip-flop circuit; and a second buffer circuit including a pair of n-channel MOS transistors having conduction channels connected in series between a positive potential source and a negative potential source, the gate of one of said transistors receiving a reference voltage and the gate of the other of said transistors being connected to the positive potential source, said transistors having a junction connected to a second of said nodes of said flip-flop circuit.
Claim 2
Dependent Claim
281 words
A sense amplifier comprising: a flip-flop circuit including two n-channel MOS transistors having a common source and two p-channel MOS transistors having a common source; said n-channel transistors and said p-channel transistors forming pairs, each pair having a conduction channel connected in series and having a common gate connected to the node of the opposite pair of said n-channel transistor and said p-channel transistor; a first switching circuit for switching the polarity of the potential supplied to said common source of said n-channel transistors of said flip-flop circuit; a second switching circuit for switching the polarity of the potential supplied to said common source of said p-channel transistors of said flip-flop circuit; wherein the polarity of the potential at the common sources is inverted in response to the transition between a stand-by sequence and a latching operation; a first buffer circuit including a pair of n-channel MOS transistors having conduction channels connected in series between a positive potential source and a negative potential source, the gate of one of said transistors receiving read-out voltage signals from memory cells and the gate of the other of said transistors being connected to the positive potential source, said transistors having a junction connected to a first of said nodes of said flip-flop circuit; and a second buffer circuit including a pair of n-channel MOS transistors having conduction channels connected in series between a positive potential source and a negative potential source, the gate of one of said transistors receiving a reference voltage and the gate of the other of said transistors being connected to the positive potential source, said transistors having a junction connected to a second of said nodes of said flip-flop circuit.
Claim 3
Dependent Claim
106 words
A sence amplifier as set forth in claim 1, wherein each of said first and second switching circuits comprises a CMOS inverter having a conduction channel connected between a positive potential source and a negative potential source, wherein said CMOS inverter comprising said first switching circuit comprises a gate for receiving a first clock signal and a junction connected to said common source of said n-channel transistors of said flip-flop circuit, and wherein said CMOS inverter comprising said second switching circuit comprises a gate for receiving a second clock signal and a junction connected to said common source of said p-channel transistors of said flip-flop circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-09 | 1989-06-10 | 1989-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-09 | 1993-06-10 | 1993-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-09 | 1997-06-10 | 1997-12-10 | $7700.00 | Window Closed / Lapsed |