US4054864A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and device for the storage of analog signals
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1975-09-15
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Granted: 1977-10-18
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Expires: 1995-09-15
Abstract
Abstract In a method and a device for storing analog signals in integrated circuit elements, the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor. After discrete sampling of the analog signal has been performed at N points, the N amplitudes corresponding to the N points are stored in N transistors in the form of a threshold voltage.
Inventors
- 👤 Luc Audaire
- 👤 Joseph Borel
- 👤 Vincent LE Goascoz
- 👤 Robert Poujois
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:44
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/163; G06G7/19; G06G7/1907; G11; G11C; G11C27/00; G11C27/005
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
117 words
A method for storing analog signals in integrated circuit memory elements, wherein the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor, comprising the steps of performing a discrete sampling of an analog signal at N points, applying N writing voltages having values which are proportional to those of each point of the sampled signal to be recorded between the gate and the inversion channel of the multiple dielectric layer transistors which constitute said memory elements, the value of the analog signal at N points being stored in the form of a corresponding threshold voltage in each of said transistors.
Claim 2
Independent Claim
117 words
A method for storing analog signals in integrated circuit memory elements, wherein the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor, comprising the steps of performing a discrete sampling of an analog signal at N points, applying N writing voltages having values which are proportional to those of each point of the sampled signal to be recorded between the gate and the inversion channel of the multiple dielectric layer transistors which constitute said memory elements, the value of the analog signal at N points being stored in the form of a corresponding threshold voltage in each of said transistors.
References Cited (Backward Citations)
US3860916A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-17 | 1981-04-18 | 1981-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-17 | 1985-04-18 | 1985-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-17 | 1989-04-18 | 1989-10-18 | $7700.00 | Window Closed / Lapsed |