US5506813A
Expired / Lapsed
US
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Semiconductor apparatus and method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1994-04-29
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Granted: 1996-04-09
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Expires: 2014-04-29
Abstract
Abstract In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors arranged in a matrix and having any one of four thresholds constitute banks in a column direction. The banks constitute memory cell arrays. A main bit line of Al is connected to three sub-bit lines via first selection transistors. A main ground line of Al is connected to two sub-ground lines via second selection transistors. Bank selection lines and word lines are formed to cross the main bit line and main ground line. Gates of the selection transistors are connected to the selection lines, and one selection line is connected to one selection transistor. Each of the sub-bit lines and sub-ground lines has a column of memory transistors which constitute a bank. A separation region (not shown) of a silicon oxide film, etc. is formed between the memory cell arrays to prevent leak current. Thereby, an information amount per one element can be made equal to a plural-bit information amount, and the bit data capacity can be increased.
Inventors
- 👤 Yoshio Mochizuki
- 👤 Hideo Kato
- 👤 Nobutake Sugiura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:29
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C16/00; G11C16/02; G11C16/04; G11C16/0491; G11C16/06; G11C16/24; G11C7/00; G11C7/18
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
325 words
A semiconductor memory apparatus comprising: a semiconductor substrate; a plurality of sub-bit lines provided on said semiconductor substrate; a plurality of sub-ground lines provided on said semiconductor substrate and arranged alternately with said sub-bit lines; a plurality of memory cells comprising a plurality of memory transistors arranged in a matrix, said memory transistors having drains connected to said sub-bit lines and sources connected to said sub-ground lines, said plurality of memory cells constituting a plurality of memory cell array blocks each comprising at least three memory transistors, each of three memory transistors within one of said memory, cell array blocks having threshold values different from one another; means for electrically separating one of said memory, cell array, blocks from another of said memory cell array blocks; first selection transistors formed on said semiconductor substrate and connected to said sub-bit lines; a second selection transistors formed on said semiconductor substrate and connected to said sub-ground lines; a plurality of word lines connected to gates of said memory transistors and crossing said sub-bit lines and sub-ground lines; a plurality of first selection lines connected to gates of said first selection transistors and crossing said sub-bit lines; a plurality of second selection lines connected to gates of said second selection transistors and crossing said sub-ground lines; main bit lines each connected to at least three of said sub-bit lines via said first selection transistors; and main ground lines each connected to at least two of said sub-ground lines via said second selection transistors, wherein one of said sub-bit lines is selected by one of said first selection transistors, one of said sub-ground lines is selected by one of said second selection transistors, and said first selection transistor connected to a predetermined one of said main bit lines is respectively connected to said first selection lines and said second selection transistors connected to a predetermined one of said main ground lines is respectively connected to said second selection lines.
Claim 2
Dependent Claim
325 words
A semiconductor memory apparatus comprising: a semiconductor substrate; a plurality of sub-bit lines provided on said semiconductor substrate; a plurality of sub-ground lines provided on said semiconductor substrate and arranged alternately with said sub-bit lines; a plurality of memory cells comprising a plurality of memory transistors arranged in a matrix, said memory transistors having drains connected to said sub-bit lines and sources connected to said sub-ground lines, said plurality of memory cells constituting a plurality of memory cell array blocks each comprising at least three memory transistors, each of three memory transistors within one of said memory, cell array blocks having threshold values different from one another; means for electrically separating one of said memory, cell array, blocks from another of said memory cell array blocks; first selection transistors formed on said semiconductor substrate and connected to said sub-bit lines; a second selection transistors formed on said semiconductor substrate and connected to said sub-ground lines; a plurality of word lines connected to gates of said memory transistors and crossing said sub-bit lines and sub-ground lines; a plurality of first selection lines connected to gates of said first selection transistors and crossing said sub-bit lines; a plurality of second selection lines connected to gates of said second selection transistors and crossing said sub-ground lines; main bit lines each connected to at least three of said sub-bit lines via said first selection transistors; and main ground lines each connected to at least two of said sub-ground lines via said second selection transistors, wherein one of said sub-bit lines is selected by one of said first selection transistors, one of said sub-ground lines is selected by one of said second selection transistors, and said first selection transistor connected to a predetermined one of said main bit lines is respectively connected to said first selection lines and said second selection transistors connected to a predetermined one of said main ground lines is respectively connected to said second selection lines.
Claim 3
Dependent Claim
24 words
A semiconductor memory apparatus according to claim 1, wherein said means for electrically separating comprises an insulation oxide film formed on said semiconductor substrate.
Claim 4
Dependent Claim
70 words
The semiconductor memory apparatus according to claim 2, wherein said semiconductor substrate is provided with a peripheral circuit region, a device separation insulating oxide film is provided between the peripheral circuit region and a region where the memory cell arrays are formed, and the thickness of the device separation insulating oxide film is equal to or greater than the thickness of the insulation oxide film formed on said semiconductor substrate.
Claim 5
Dependent Claim
54 words
A semiconductor memory apparatus according to claim 1, further comprising a sense amplifier provided with at least two reference signals and with a data signal output from said plurality of memory cells, said sense amplifier providing an output signal based on a comparison between said at least two reference signals and said data signal.
Claim 6
Dependent Claim
298 words
A semiconductor memory comprising: a semiconductor substrate; a plurality of sub-bit lines provided on said semiconductor substrate; a plurality of sub-ground lines provided on said semiconductor substrate and arranged alternately with said sub-bit lines; a plurality of memory transistors arranged in a matrix, said memory transistors having drains connected to said sub-bit lines and sources connected to said sub-ground lines, said plurality of memory transistors constituting a plurality of memory cell array blocks each comprising at least three memory transistors; means for electrically separating one of said memory cell array blocks from another of said memory cell array blocks; first selection transistors formed on said semiconductor substrate and connected to said sub-bit lines; a second selection transistors formed on said semiconductor substrate and connected to said sub-ground lines; a plurality of word lines connected to gates of said memory transistors and crossing said sub-bit lines and sub-ground lines; a plurality of first selection lines connected to gates of said first selection transistors and crossing said sub-bit lines; a plurality of second selection lines connected to gates of said second selection transistors and crossing said sub-ground lines; main bit lines each connected to at least three of said sub-bit lines via said first selection transistors; and main ground lines each connected to at least two of said sub-ground lines via said second selection transistors, wherein one of said sub-bit lines is selected by one of said first selection transistors, one of said sub-ground lines is selected by one of said second selection transistors, and said first selection transistor connected to a predetermined one of said main bit lines is respectively connected to said first selection lines and said second selection transistors connected to a predetermined one of said main ground lines is respectively connected to said second selection lines.
Claim 7
Dependent Claim
298 words
A semiconductor memory comprising: a semiconductor substrate; a plurality of sub-bit lines provided on said semiconductor substrate; a plurality of sub-ground lines provided on said semiconductor substrate and arranged alternately with said sub-bit lines; a plurality of memory transistors arranged in a matrix, said memory transistors having drains connected to said sub-bit lines and sources connected to said sub-ground lines, said plurality of memory transistors constituting a plurality of memory cell array blocks each comprising at least three memory transistors; means for electrically separating one of said memory cell array blocks from another of said memory cell array blocks; first selection transistors formed on said semiconductor substrate and connected to said sub-bit lines; a second selection transistors formed on said semiconductor substrate and connected to said sub-ground lines; a plurality of word lines connected to gates of said memory transistors and crossing said sub-bit lines and sub-ground lines; a plurality of first selection lines connected to gates of said first selection transistors and crossing said sub-bit lines; a plurality of second selection lines connected to gates of said second selection transistors and crossing said sub-ground lines; main bit lines each connected to at least three of said sub-bit lines via said first selection transistors; and main ground lines each connected to at least two of said sub-ground lines via said second selection transistors, wherein one of said sub-bit lines is selected by one of said first selection transistors, one of said sub-ground lines is selected by one of said second selection transistors, and said first selection transistor connected to a predetermined one of said main bit lines is respectively connected to said first selection lines and said second selection transistors connected to a predetermined one of said main ground lines is respectively connected to said second selection lines.
Claim 8
Dependent Claim
18 words
A semiconductor memory according to claim 5, wherein a plurality of said memory transistors each store multi-bit data.
Claim 9
Dependent Claim
39 words
A semiconductor memory according to claim 5, further comprising a sense amplifier coupled to a memory transistor via a main bit line, wherein said sense amplifier provides a drive signal to said memory transistor during a data reading operation.
Claim 10
Dependent Claim
24 words
A semiconductor memory apparatus according to claim 6, wherein said means for electrically separating comprises an insulation oxide film formed on said semiconductor substrate.
Claim 11
Dependent Claim
54 words
A semiconductor memory apparatus according to claim 8, further comprising a sense amplifier provided with at least two reference signals and with a data signal output from said plurality of memory cells, said sense amplifier providing an output signal based on a comparison between said at least two reference signals and said data signal.
Claim 12
Dependent Claim
70 words
The semiconductor memory apparatus according to claim 8, wherein said semiconductor substrate is provided with a peripheral circuit region, a device separation insulating oxide film is provided between the peripheral circuit region and a region where the memory cell arrays are formed, and the thickness of the device separation insulating oxide film is equal to or greater than the thickness of the insulation oxide film formed on said semiconductor substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |