EP0109854A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory devices and methods for making the same
Assignee: American Microsystems Holding Corp
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Filing: 1983-11-21
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Granted: —
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Expires: 2003-11-21
Abstract
Abstract An array of MOS transistors (30) is formed in a semiconductor substrate having a plurality of continuous diffused lines (bit lines) (7-3, 7-4, 7-5 and 7-6) serving as the source and drain regions of a plurality of MOS transistors. A plurality of conductive word lines (33, 133) are formed over the plurality of diffused lines, crossing the diffused lines at substantially right angles, with each conductive word line serving as the gates of a plurality of MOS transistors. Each transistor of the memory array is formed in a region containing two continuous diffused lines and a single word line. A single electrical contact (36-3, 4,. 5, 6) to a bit line is formed for each such diffused line.
Inventors
- 👤 Tarsaim Lal Batra
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 18:41
CPC Classifications
H; H10; H10B; H10B20/00; H10B69/00
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
211 words
A semiconductor memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a first doped region of a second conductivity type opposite the first conductivity type; a second doped region of the second conductivity type; a plurality of channel regions located between the first and second doped regions; a plurality of conductive lines each located above and insulated from an.associated one of the channel regions by a first insulation layer; and an additional N channel and an additional P channel transistor having a source, a drain, a gate and a channel, the source and drain of said additional transistor not being formed as part of the first and second doped regions the first doped region serving as the source of each cell, the second doped region serves as the drain of each cell, each conductive line serving as the gate of one of the plurality of cells, and the portion of the substrate between the first and second doped regions and beneath each conductive line serving as the channel of one of the plurality of cells.
Claim 2
Dependent Claim
211 words
A semiconductor memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a first doped region of a second conductivity type opposite the first conductivity type; a second doped region of the second conductivity type; a plurality of channel regions located between the first and second doped regions; a plurality of conductive lines each located above and insulated from an.associated one of the channel regions by a first insulation layer; and an additional N channel and an additional P channel transistor having a source, a drain, a gate and a channel, the source and drain of said additional transistor not being formed as part of the first and second doped regions the first doped region serving as the source of each cell, the second doped region serves as the drain of each cell, each conductive line serving as the gate of one of the plurality of cells, and the portion of the substrate between the first and second doped regions and beneath each conductive line serving as the channel of one of the plurality of cells.
Claim 3
Dependent Claim
318 words
A semiconductor memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type opposite the first conductivity type, and a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a first doped region of a second conductivity type opposite the first conductivity type; a second doped region of the second conductivity type; a plurality of channel regions located between the first and second doped regions; a well region of the second conductivity type located in the substrate; a third and a fourth doped region of the second conductivity type formed within the substrate; a fifth and a sixth doped region of the first conductivity type formed within the well region; a plurality of floating gates each located above and insulated from an associated channel region by a first insulation layer; and a plurality of conductive lines each located above and insulated from an associated one of the floating gates by a second insulation layer; the first doped region serving as the source of each cell, the second doped region serving as the drain of each cell, each conductive line serving as the control gate of one of the plurality of cells, the portion of the substrate between the first and second doped regions and beneath each conductive line serving as the channel of one of the plurality of cells, the third doped region serving as the source of the first transistor, the fourth doped region serving as the drain of the first transistor, the fifth doped region serving as the source of the second transistor, and the sixth doped region serving as the drain of the second transistor.
Claim 4
Dependent Claim
318 words
A semiconductor memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type opposite the first conductivity type, and a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a first doped region of a second conductivity type opposite the first conductivity type; a second doped region of the second conductivity type; a plurality of channel regions located between the first and second doped regions; a well region of the second conductivity type located in the substrate; a third and a fourth doped region of the second conductivity type formed within the substrate; a fifth and a sixth doped region of the first conductivity type formed within the well region; a plurality of floating gates each located above and insulated from an associated channel region by a first insulation layer; and a plurality of conductive lines each located above and insulated from an associated one of the floating gates by a second insulation layer; the first doped region serving as the source of each cell, the second doped region serving as the drain of each cell, each conductive line serving as the control gate of one of the plurality of cells, the portion of the substrate between the first and second doped regions and beneath each conductive line serving as the channel of one of the plurality of cells, the third doped region serving as the source of the first transistor, the fourth doped region serving as the drain of the first transistor, the fifth doped region serving as the source of the second transistor, and the sixth doped region serving as the drain of the second transistor.
Claim 5
Dependent Claim
246 words
A semiconductor memory device having a plurality of R x S cells, each cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a core region within the substrate within which are formed said plurality of cells; a field region surrounding the core region; a field oxide layer formed on the substrate in the field region; a plurality of R+l doped regions of a second conductivity type opposite the first conductivity type formed within the core region; a plurality of S conductive lines each crossing each of the plurality of doped regions; an insulation layer formed between the plurality of doped regions and the plurality of conductive lines, thereby providing electrical insulation therebetween; and an additional N channel and an additional P channel transistor having a source, a drain, a gate and a channel, the sources and drains of the additional transistor not being formed as part of the first and second doped regions and each cell being formed by one of the plurality of doped regions serving as a source, an associated one of the first plurality of doped regions serving as a drain, an associated one of the plurality of conductive lines serving as a gate; and that portion of the substrate located between the source and the drain and beneath the gate serving as said channel.
Claim 6
Dependent Claim
246 words
A semiconductor memory device having a plurality of R x S cells, each cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a core region within the substrate within which are formed said plurality of cells; a field region surrounding the core region; a field oxide layer formed on the substrate in the field region; a plurality of R+l doped regions of a second conductivity type opposite the first conductivity type formed within the core region; a plurality of S conductive lines each crossing each of the plurality of doped regions; an insulation layer formed between the plurality of doped regions and the plurality of conductive lines, thereby providing electrical insulation therebetween; and an additional N channel and an additional P channel transistor having a source, a drain, a gate and a channel, the sources and drains of the additional transistor not being formed as part of the first and second doped regions and each cell being formed by one of the plurality of doped regions serving as a source, an associated one of the first plurality of doped regions serving as a drain, an associated one of the plurality of conductive lines serving as a gate; and that portion of the substrate located between the source and the drain and beneath the gate serving as said channel.
Claim 7
Dependent Claim
400 words
A semiconductor memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type opposite said first conductivity type, and a plurality of R x S cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a core region within the substrate within which are formed the plurality of cells; a peripheral region within the substrate; a field region surrounding the core region; a field oxide layer formed on the substrate in the field region; a plurality of R+l doped regions of a second conductivity type opposite the first conductivity type formed within the core region; a plurality of S conductive lines each crossing each of the first plurality of doped regions; a plurality of R x S floating gates each floating gate being unequally associated with one of the R x S portions of the S conductive lines lying between the R+I doped regions, and each floating gate being insulated from the substrate, the plurality of Rl doped regions and the plurality of S conductive lines; an insulation layer formed between the first plurality of doped regions and the plurality of conductive lines, thereby providing electrical insulation therebetween; a well region of the second conductivity type formed in the peripheral region; a third and a fourth doped region of the second conductivity type formed in the peripheral region; and a fifth and a sixth doped region of the first conductivity type formed in the well region; wherein each cell is formed by one of the plurality of doped regions serving as a source, an associated one of the first plurality of doped regions serving as a drain, an associated one of the plurality of conductive lines serving as a gate, and that portion of the substrate located between the source and the drain and beneath the gate serving as the channel, and wherein the third doped region serves as the source of the first transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor and the sixth doped region serves as the drain of the second transistor.
Claim 8
Dependent Claim
400 words
A semiconductor memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type opposite said first conductivity type, and a plurality of R x S cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a core region within the substrate within which are formed the plurality of cells; a peripheral region within the substrate; a field region surrounding the core region; a field oxide layer formed on the substrate in the field region; a plurality of R+l doped regions of a second conductivity type opposite the first conductivity type formed within the core region; a plurality of S conductive lines each crossing each of the first plurality of doped regions; a plurality of R x S floating gates each floating gate being unequally associated with one of the R x S portions of the S conductive lines lying between the R+I doped regions, and each floating gate being insulated from the substrate, the plurality of Rl doped regions and the plurality of S conductive lines; an insulation layer formed between the first plurality of doped regions and the plurality of conductive lines, thereby providing electrical insulation therebetween; a well region of the second conductivity type formed in the peripheral region; a third and a fourth doped region of the second conductivity type formed in the peripheral region; and a fifth and a sixth doped region of the first conductivity type formed in the well region; wherein each cell is formed by one of the plurality of doped regions serving as a source, an associated one of the first plurality of doped regions serving as a drain, an associated one of the plurality of conductive lines serving as a gate, and that portion of the substrate located between the source and the drain and beneath the gate serving as the channel, and wherein the third doped region serves as the source of the first transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor and the sixth doped region serves as the drain of the second transistor.
Claim 9
Dependent Claim
28 words
A semiconductor memory device as claimed in claim 3 or 4 wherein each of the plurality of R+l doped regions is substantially covered by a second insulation layer.
Claim 10
Dependent Claim
22 words
A semiconductor memory device as claimed in claim 5 wherein the second insulation layer is substantially thicker than the first-mentioned insulation layer.
Claim 11
Dependent Claim
33 words
A semiconductor memory device as claimed in any preceding claim wherein each of the plurality of cells is surrounded by a field region, the field region being covered by a thick field oxide.
Claim 12
Independent Claim
290 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type opposite the first conductivity type, and a plurality of cells, each cell comprising an MOS memory transistor having a source, a drain; a gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming in the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; . forming in said substrate a well region of the second conductivity type; forming in said substrate a third and a fourth doped region of the second conductivity type; forming in the well region a fifth and a sixth doped region of the first conductivity type; forming a relatively thin insulation layer over selected portions of the first and second doped regions, the well region, and over that portion of the substrate located between the first and second doped regions; and forming a plurality of conductive gate regions on the relatively thin insulation layer; wherein the first doped region forms the source of each MOS memory transistor, the second doped region forms the drain of each MOS memory transistor, the portion of the substrate beneath each gate region serves as the channel of its associated MOS transistor, the third doped region serves as the source of the transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor and the sixth doped region serves as the drain of the second transistor.
Claim 13
Independent Claim
290 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type opposite the first conductivity type, and a plurality of cells, each cell comprising an MOS memory transistor having a source, a drain; a gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming in the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; . forming in said substrate a well region of the second conductivity type; forming in said substrate a third and a fourth doped region of the second conductivity type; forming in the well region a fifth and a sixth doped region of the first conductivity type; forming a relatively thin insulation layer over selected portions of the first and second doped regions, the well region, and over that portion of the substrate located between the first and second doped regions; and forming a plurality of conductive gate regions on the relatively thin insulation layer; wherein the first doped region forms the source of each MOS memory transistor, the second doped region forms the drain of each MOS memory transistor, the portion of the substrate beneath each gate region serves as the channel of its associated MOS transistor, the third doped region serves as the source of the transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor and the sixth doped region serves as the drain of the second transistor.
Claim 14
Independent Claim
341 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type opposite said first conductivity type, and a plurality of cells, each cell comprising an MOS memory transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming a patterned field oxide layer on the surface of the substrate, thereby leaving selected portions of the substrate free from the field oxide; forming in said substrate a well region of the second conductivity type; forming in the selected portions of the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thick insulation layer over a substantial portion of the first and second doped regions; forming in the substrate a third and a fourth doped region of the second conductivity type; forming in the well region a fifth and a sixth doped region of the first conductivity type; forming a relatively thin insulation layer over those portions of the first and second doped regions which are not covered by the relatively thick insulation layer and over that portion of the substrate located between the first and second doped regions; and forming a plurality of conductive gate regions on the relatively thin insulation layer; wherein the first doped region forms the source of each MOS transistor, the second doped region forms the drain of each MOS transistor, and the portion of the substrate beneath each gate region serves as the channel of its associated MOS transistor, the third doped region serves as the source of the first transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor and the sixth doped region serves as the drain of the second transistor.
Claim 15
Independent Claim
341 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type opposite said first conductivity type, and a plurality of cells, each cell comprising an MOS memory transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming a patterned field oxide layer on the surface of the substrate, thereby leaving selected portions of the substrate free from the field oxide; forming in said substrate a well region of the second conductivity type; forming in the selected portions of the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thick insulation layer over a substantial portion of the first and second doped regions; forming in the substrate a third and a fourth doped region of the second conductivity type; forming in the well region a fifth and a sixth doped region of the first conductivity type; forming a relatively thin insulation layer over those portions of the first and second doped regions which are not covered by the relatively thick insulation layer and over that portion of the substrate located between the first and second doped regions; and forming a plurality of conductive gate regions on the relatively thin insulation layer; wherein the first doped region forms the source of each MOS transistor, the second doped region forms the drain of each MOS transistor, and the portion of the substrate beneath each gate region serves as the channel of its associated MOS transistor, the third doped region serves as the source of the first transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor and the sixth doped region serves as the drain of the second transistor.
Claim 16
Independent Claim
284 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a first transistor having a channel of a first conductivity type, a second conductivity type opposite the first conductivity type, and a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming in the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thin insulation layer over selected portions of the first and second doped regions and over that portion of the substrate located between the first and second doped regions; and forming a plurality of conductive gate regions on the relatively thin insulation layer; forming in the substrate a well region of the second conductivity type; forming in the substrate a third and a fourth doped region of the second conductivity type; and forming in the well region a fifth and a sixth doped region of the first conductivity type; wherein the first doped region forms the source of each MOS transistor, the second doped region forms the drain of each MOS transistor, and the portion of the substrate beneath each gate region serves as the channel of its associated MOS transistor, and the third doped region serves as the source of the first transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor and the sixth doped region serves as the drain of the second transistor.
Claim 17
Independent Claim
284 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a first transistor having a channel of a first conductivity type, a second conductivity type opposite the first conductivity type, and a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming in the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thin insulation layer over selected portions of the first and second doped regions and over that portion of the substrate located between the first and second doped regions; and forming a plurality of conductive gate regions on the relatively thin insulation layer; forming in the substrate a well region of the second conductivity type; forming in the substrate a third and a fourth doped region of the second conductivity type; and forming in the well region a fifth and a sixth doped region of the first conductivity type; wherein the first doped region forms the source of each MOS transistor, the second doped region forms the drain of each MOS transistor, and the portion of the substrate beneath each gate region serves as the channel of its associated MOS transistor, and the third doped region serves as the source of the first transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor and the sixth doped region serves as the drain of the second transistor.
Claim 18
Independent Claim
351 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type, and a plurality of cells, each cell comprising a MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the ,teps of: forming a patterned field oxide layer on the surface of the substrate, thereby leaving selected portions of the substrate free from said field oxide; .forming in the selected portions of the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thick insulation layer over a substantial portion of the first and second doped regions; forming in the substrate a well region of the second conductivity type; forming in the substrate a third and a fourth doped region of the second conductivity type; forming in the well region a fifth and a sixth doped region of the first conductivity type; forming a relatively thin first insulation layer over those portions of the first and second doped regions which are not covered by the relatively thick insulation layer and over that portion of the substrate located between the first and second doped regions; forming a plurality floating gate regions on the first insulation layer; and forming a plurality conductive gate regions on the relatively thin insulation layer; wherein the first doped region forms the source of each MOS transistor, the second doped region forms the drain of each MOS transistor, and the portion of the substrate beneath each gate region serves as the channel of its associated MOS transistor, and the third doped region serves as the source of the first transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor, and the sixth doped region serves as the drain of the second transistor.
Claim 19
Independent Claim
351 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a first transistor having a channel of a first conductivity type, a second transistor having a channel of a second conductivity type, and a plurality of cells, each cell comprising a MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the ,teps of: forming a patterned field oxide layer on the surface of the substrate, thereby leaving selected portions of the substrate free from said field oxide; .forming in the selected portions of the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thick insulation layer over a substantial portion of the first and second doped regions; forming in the substrate a well region of the second conductivity type; forming in the substrate a third and a fourth doped region of the second conductivity type; forming in the well region a fifth and a sixth doped region of the first conductivity type; forming a relatively thin first insulation layer over those portions of the first and second doped regions which are not covered by the relatively thick insulation layer and over that portion of the substrate located between the first and second doped regions; forming a plurality floating gate regions on the first insulation layer; and forming a plurality conductive gate regions on the relatively thin insulation layer; wherein the first doped region forms the source of each MOS transistor, the second doped region forms the drain of each MOS transistor, and the portion of the substrate beneath each gate region serves as the channel of its associated MOS transistor, and the third doped region serves as the source of the first transistor and the fourth doped region serves as the drain of the first transistor, the fifth doped region serves as the source of the second transistor, and the sixth doped region serves as the drain of the second transistor.
References Cited (Backward Citations)
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