Semiconductor read only memory with paralleled selecting transistors for higher speed

Claim 1

A semiconductor read only memory including a plurality of word lines disposed in parallel, the semiconductor read only memory having a plurality of units, each of the plurality of units comprising: a first main bit line and a second main bit line which cross the word lines, a first sub-bit line, a second sub-bit line, a third sub-bit line, and a fourth sub-bit line which are disposed substantially in parallel to the first and second main bit lines, each of the first, second, third and fourth sub-bit lines having a first end and a second end; four memory cell columns, each including a plurality of memory cells connected in parallel between respective adjacent two of the first, second, third and fourth sub-bit lines; and a plurality of bank selecting switches for selecting one of the four memory cell columns; wherein to the first main bit line, the first ends of the first sub-bit line and the third sub-bit line are connected, and to the second main bit line, the second ends of the second sub-bit line and the fourth sub-bit line are connected, wherein first and second ones of the bank selecting switches are disposed in parallel between the first main bit line and the first sub-bit line, and third and fourth ones of the bank selecting switches are disposed in parallel between the second main bit line and the fourth sub-bit line, and wherein a fifth one of the bank selecting switches is disposed between the first main bit line and the third sub-bit line, and a sixth one of the bank selecting switches is disposed between the second main bit line and the second sub-bit line.