Memory with reference voltage generator

Claim 2

A read only memory having a plurality of memory cells arranged in columns and rows, the memory also comprising: the memory cells being capable of providing an output having more than two states; a plurality of comparators selectively coupled to the columns; a plurality of reference sources arranged in groups wherein each group is coupled to a different comparator, each of the reference sources is a transistor connected in a source follower configuration and each of the transistors is a field effect transistor and at least two of the transistors have threshold voltages different from each other; and logic means coupled to the comparators to receive an output provided by each comparator, the logic means providing digital bits representative of the state of a selected memory cell.

Claim 3

The memory of claim 1 wherein at least a predetermined one of the reference sources is enabled when one of the rows in the memory is selected.

Claim 4

The memory of claim 1 wherein the memory cells are capable of storing at least four states.

Claim 5

The memory of claim 3 wherein the memory cells each have a transistor connected in a source follower configuration.

Claim 6

The memory of claim 4 wherein said each group of reference sources is arranged as a column in the memory.

Claim 7

A memory array having a plurality of storage cells wherein each storage cell is capable of storing m states where m is greater than two and where the m states appear as voltage levels, the memory array having n reference sources where n+1=m, the reference sources being arranged in columns and rows, and having a number of columns equivalent to n wherein each column has a plurality of reference sources equal to one of the states, the number of rows being equal to the number of rows found in the memory array wherein each row of reference sources provides n references, and at least n comparators, each comparator being coupled to a different column of reference sources and the comparators being controllably coupled to a selected memory column.

Claim 8

A memory array having a plurality of storage cells wherein each storage cell is capable of storing m states where m is greater than two and where the m states appear as voltage levels, the memory array having n reference sources where n+1=m, the reference sources being arranged in columns and rows, and having a number of columns equivalent to n wherein each column has a plurality of reference sources equal to one of the states, the number of rows being equal to the number of rows found in the memory array wherein each row of reference sources provides n references, and at least n comparators, each comparator being coupled to a different column of reference sources and the comparators being controllably coupled to a selected memory column.

Claim 9

The memory array of claim 6 wherein the reference sources are enabled by a row select command which also selects a row in the memory array, each of the reference sources being a transistor connected in a source follower configuration and having a predetermined threshold voltage to render a desired reference voltage.

Claim 10

A memory having a plurality of memory cells arranged in rows and columns, comprising: a transistor connected in a source follower configuration being in each memory cell and having a threshold voltage so that at least one transistor has a threshold voltage different from another of the transistors so that more than two states can be represented by a memory cell; reference means arranged adjacent the memory cells for providing reference voltage to be compared with the states of the memory cells, the reference means being arranged in rows and columns so that each column provides a predetermined reference voltage which differs from an adjacent column's reference voltage; and comparator means selectively coupled to a memory cell and coupled to the reference means to provide an output indicative of the states stored in the memory cell which was selectively coupled to the comparator.

Claim 11

A memory having a plurality of memory cells arranged in rows and columns, comprising: a transistor connected in a source follower configuration being in each memory cell and having a threshold voltage so that at least one transistor has a threshold voltage different from another of the transistors so that more than two states can be represented by a memory cell; reference means arranged adjacent the memory cells for providing reference voltage to be compared with the states of the memory cells, the reference means being arranged in rows and columns so that each column provides a predetermined reference voltage which differs from an adjacent column's reference voltage; and comparator means selectively coupled to a memory cell and coupled to the reference means to provide an output indicative of the states stored in the memory cell which was selectively coupled to the comparator.

Claim 12

A reference voltage generator for a digital memory having a plurality of memory cells arranged in rows and columns, the memory cells being capable of storing more than two states, comprising: a plurality of reference transistors connected in a source follower configuration for each reference voltage required and arranged in rows and columns wherein each said transistor in a selected row is enabled by a row select signal so that said transistors are only enabled when the memory cells in the selected row are being accessed; and means for comparing contents of the memory cells with said transistor so that the state of the contents of the memory cells can be determined.

Claim 13

A reference voltage generator for a digital memory having a plurality of memory cells arranged in rows and columns, the memory cells being capable of storing more than two states, comprising: a plurality of reference transistors connected in a source follower configuration for each reference voltage required and arranged in rows and columns wherein each said transistor in a selected row is enabled by a row select signal so that said transistors are only enabled when the memory cells in the selected row are being accessed; and means for comparing contents of the memory cells with said transistor so that the state of the contents of the memory cells can be determined.