US5930638A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a low parasitic resistor on ultrathin silicon on insulator
Assignee: PSemi Corp
•
Filing: 1997-08-19
•
Granted: 1999-07-27
•
Expires: 2017-08-19
Abstract
Abstract A diffused resistor and a method for making the diffused resistor are disclosed. The diffused resistor is formed in a substantially pure portion of the thin semiconductor layer that is formed on an insulating substrate. The thin semiconductor layer has low a number of defects and mid-band gap states. This portion may be located in an electrically isolated region of the thin semiconductor layer. A resistive region is used to provide the resistance of the diff-used resistor. Contact regions are provided continguous with the the resistive region. The diff-used resistor can be formed by themselves or in conjunction with other circuit elements, such as a MOSFET, for example. Accordingly, also disclosed is a method for making the diffused resitor in conjunction with a MOSFET. The diffused resistor and the MOSFET are formed in electrically isolated semiconductor islands. The electrically isolated semiconductor islands are formed from the high quality thin semiconductor layer. Both non-silicide and silicide processes are disclosed. Also disclosed is a differential amplifier circuit that uses the disclosed diffused resistor embodiments.
Inventors
- 👤 Ronald E. Reedy
- 👤 Mark L. Burgener
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:24
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2921; H10B; H10B10/00; H10B10/15; H10D; H10D1/00; H10D1/40; H10D1/43; H10D1/47; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D30/6758; H10D30/6759; H10D86/00; H10D86/01; H10D86/03; H10D86/201; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/38; H10P14/3822; Y; Y10; Y10S; Y10S148/00; Y10S148/136
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
150 words
A method for forming a diffused resistor comprising the steps of: providing an insulating substrate; forming a thin semiconductor layer on the insulating substrate wherein the thin semiconductor layer has a maximum fixed charge density of no more than about 5×10 11 cm -2 ; providing any resistor implants in a resistive region of the thin semiconductor layer wherein the any resistor implants are for setting a resistance of the diffused resistor; preventing any implants other than the any resistor implants from being provided in the resistive region; forming in the thin semiconductor layer a first contact region and a second contact region wherein the first contact region is electrically coupled to the resistive region by being contiguous with a first portion of the resistive region and wherein the second contact region is electrically coupled to the resistive region by being contiguous with a second portion of the resistive region.
Claim 2
Independent Claim
150 words
A method for forming a diffused resistor comprising the steps of: providing an insulating substrate; forming a thin semiconductor layer on the insulating substrate wherein the thin semiconductor layer has a maximum fixed charge density of no more than about 5×10 11 cm -2 ; providing any resistor implants in a resistive region of the thin semiconductor layer wherein the any resistor implants are for setting a resistance of the diffused resistor; preventing any implants other than the any resistor implants from being provided in the resistive region; forming in the thin semiconductor layer a first contact region and a second contact region wherein the first contact region is electrically coupled to the resistive region by being contiguous with a first portion of the resistive region and wherein the second contact region is electrically coupled to the resistive region by being contiguous with a second portion of the resistive region.
Claim 3
Dependent Claim
73 words
The method of claim 1, further comprising the steps of: forming an electrically isolated portion of the thin semiconductor layer wherein the electrically isolated portion of the thin semiconductor layer has the maximum fixed charge density of no more than about 5×10 11 cm -2 ; after forming the electrically isolated portion of the thin semiconductor layer, forming the first and second contact regions and the resistive region in the electrically isolated portion.
Claim 4
Dependent Claim
15 words
The method of claim 1, wherein the thin semiconductor layer comprises a thin silicon layer.
Claim 5
Dependent Claim
19 words
The method of claim 1, wherein the thickness of the semiconductor layer is no more than about 1,500 angstroms.
Claim 6
Dependent Claim
21 words
The method of claim 1, wherein the thickness of the thin semiconductor layer is in a range of about 500-1500 angstroms.
Claim 7
Dependent Claim
20 words
The method of claim 1, wherein the thickness of the thin semiconductor layer is no more than about 1,100 angstroms.
Claim 8
Dependent Claim
11 words
The method of claim 1, wherein the insulating substrate comprises sapphire.
Claim 9
Dependent Claim
21 words
The method of claim 1, wherein the maximum fixed charge density is no more than about 3×10 11 cm -2 .
Claim 10
Dependent Claim
28 words
The method of claim 1, wherein the maximum fixed charge density is in a range of about 2×10 11 cm -2 to about 5×10 11 cm -2 .
Claim 11
Dependent Claim
28 words
The method of claim 1, wherein the step of providing any resistor implants in the resistive region comprises ion implanting a conductivity determining dopant into the resistive region.
Claim 12
Dependent Claim
22 words
The method of claim 10, wherein the step of providing any resistor implants in the resistive region dopes the resistive region N-type.
Claim 13
Dependent Claim
24 words
The method of claim 11, wherein the step of forming the first and second contact regions dopes the first and second contact regions N+type.
Claim 14
Dependent Claim
22 words
The method of claim 10, wherein the step of providing any resistor implants in the resistive region dopes the resistive region P-type.
Claim 15
Dependent Claim
24 words
The method of claim 13, wherein the step of forming the first and second contact regions dopes the first and second contact regions P+type.
Claim 16
Dependent Claim
28 words
The method of claim 1, wherein the step of providing any resistor implants in the resistive region comprises diffusion doping a conductivity determining dopant into the resistive region.
Claim 17
Dependent Claim
15 words
The method of claim 1, wherein no resistor implant is provided in the resistive region.
Claim 18
Dependent Claim
16 words
The method of claim 1, wherein the any resistive implants consist of a single dopant type.
Claim 19
Dependent Claim
19 words
The method of claim 1, wherein a resistance of the diffused resistor has an accuracy of ± five percent.
Claim 20
Dependent Claim
52 words
The method of claim 1, wherein prior to providing the any resistor implants in the resistive region, the resistive region has a maximum fixed charge density such that the resistive region is capable of providing sheet resistances ranging from as low as about 30 Ω/□ to as high as about 1,000,000,000 Ω/□.
Claim 21
Dependent Claim
23 words
The method of claim 1, wherein a resistance of the diffused resistor provides resistance matching to an accuracy of about ± one percent.
Claim 22
Dependent Claim
24 words
The method of claim 1, wherein dimensions of the resistive region can be as small as a lithography limit of an initial masking step.
Claim 23
Dependent Claim
28 words
The method of claim 1, wherein the diffused resistor exhibits a temperature coefficient in the range of about -350 parts per million to about -75 parts per million.
Claim 24
Dependent Claim
28 words
The method of claim 1, wherein the diffused resistor exhibits a temperature coefficient in the range of about -350 parts per million to about -150 parts per million.
Claim 25
Dependent Claim
28 words
The method of claim 1, wherein the diffused resistor exhibits a voltage coefficient in the range of about -1.2 parts per million to about -995 parts per million.
Claim 26
Dependent Claim
30 words
The method of claim 1, where in the diff used resistor exhibits a voltage coefficient in the range of about -1.2 parts per million to about -950 parts per million.
Claim 27
Dependent Claim
28 words
The method of claim 1, wherein the diffused resistor exhibits a voltage coefficient in the range of about -1.2 parts per million to about -900 parts per million.
Claim 28
Dependent Claim
62 words
The method of claim 1, further comprising the steps of: providing a silicide block over the resistive region wherein the silicide block is self-aligned with the first and second contact regions; forming a first silicide region in the first contact region after providing the silicide block; and forming a second silicide region in the second contact region after providing the silicide block.
Claim 29
Independent Claim
231 words
A method for forming a diffused resistor and a MOSFET in a thin semiconductor layer, the method comprising the steps of: providing an insulating substrate; forming the thin semiconductor layer on the insulating substrate wherein the thin semiconductor layer has a maximum fixed charge density of no more than about 5×10 11 cm -2 ; forming a first electrically isolated portion of the thin semiconductor layer and a second electrically isolated portion of the thin semiconductor layer wherein at least the first electrically isolated portion has the maximum fixed charge density of no more than about 5×10 11 cm -2 ; providing any resistor implants in a resistive region of the first electrically isolated portion of the thin semiconductor layer wherein the resistor implants are for setting a resistance of the diffused resistor; preventing any implants other than the any resistor implants from being provided in the resistive region; forming in the first electrically isolated portion of the thin semiconductor layer a first contact region and a second contact region wherein the first contact region is electrically coupled to the resistive region by being contiguous with a first portion of the resistive region and wherein the second contact region is electrically coupled to the resistive region by being contiguous with a second portion of the resistive region; forming a MOSFET in the second electrically isolated portion of the thin semiconductor layer.
Claim 30
Independent Claim
231 words
A method for forming a diffused resistor and a MOSFET in a thin semiconductor layer, the method comprising the steps of: providing an insulating substrate; forming the thin semiconductor layer on the insulating substrate wherein the thin semiconductor layer has a maximum fixed charge density of no more than about 5×10 11 cm -2 ; forming a first electrically isolated portion of the thin semiconductor layer and a second electrically isolated portion of the thin semiconductor layer wherein at least the first electrically isolated portion has the maximum fixed charge density of no more than about 5×10 11 cm -2 ; providing any resistor implants in a resistive region of the first electrically isolated portion of the thin semiconductor layer wherein the resistor implants are for setting a resistance of the diffused resistor; preventing any implants other than the any resistor implants from being provided in the resistive region; forming in the first electrically isolated portion of the thin semiconductor layer a first contact region and a second contact region wherein the first contact region is electrically coupled to the resistive region by being contiguous with a first portion of the resistive region and wherein the second contact region is electrically coupled to the resistive region by being contiguous with a second portion of the resistive region; forming a MOSFET in the second electrically isolated portion of the thin semiconductor layer.
Claim 31
Dependent Claim
103 words
The method of claim 28, wherein the step of forming the MOSFET in the second electrically isolated portion of the thin semiconductor layer comprises the steps of: forming in the second electrically isolated portion a channel of the MOSFET; forming a gate oxide adjacent to the channel; forming a gate conductor adjacent to the gate oxide; forming in the second electrically isolated portion a source of the MOSFET that is self-aligned by the gate oxide and the gate conductor; and forming in the second electrically isolated portion a drain of the MOSFET that is self-aligned by the gate oxide and the gate conductor.
Claim 32
Dependent Claim
31 words
The method of claim 29, further comprising the step of: providing the any resistor implant in the resistive region during a doping step that also dopes the channel of the MOSFET.
Claim 33
Dependent Claim
31 words
The method of claim 29, further comprising the step of: doping the first and second contact regions during a doping step that also dopes the source and drain of the MOSFET.
Claim 34
Dependent Claim
30 words
The method of claim 29, further comprising the step of forming a first sidewall spacer and a second sidewall spacer each adjacent to the gate oxide and the gate conductor.
Claim 35
Dependent Claim
43 words
The method of claim 32, wherein the step of forming the source and drain of the MOSFET comprises the step of forming a lightly doped source self-aligned by the first sidewall spacer and a lightly doped drain self-aligned by the second sidewall spacer.
Claim 36
Dependent Claim
41 words
The method of claim 33, wherein the step of forming the source comprises the step of forming a silicide region in the source and the step of forming the drain comprises the step of forming a silicide region in the drain.
Claim 37
Dependent Claim
24 words
The method of claim 29, wherein step of forming the gate conductor comprises the step of forming a silicide region in the gate conductor.
Claim 38
Dependent Claim
22 words
The method of claim 32, wherein the step of forming the sidewall spacers also forms a silicide block over the resistive region.
Claim 39
Dependent Claim
37 words
The method of claim 36, further comprising the step of forming a silicide region in each of the source, the drain and the gate conductor after the step of forming the sidewall spacers and the silicide block.
Claim 40
Dependent Claim
20 words
The method of claim 28, wherein the thin semiconductor layer has a thickness of no more than about 1,500 angstroms.
Claim 41
Dependent Claim
40 words
The method of claim 28, wherein the step of providing any resistor implants in the resistive region of the first electrically isolated portion is performed after the step of forming the first electrically isolated portion of the thin semiconductor layer.
References Cited (Backward Citations)
US3309586A
Cited
US3562425A
Cited
US3492511A
Cited
US3562608A
Cited
US3798508A
Cited
US3829881A
Cited
US3829743A
Cited
US3699544A
Cited
US4065781A
Cited
US4048350A
Cited
US4072910A
Cited
US4037140A
Cited
US4198649A
Cited
FR2380637A1
Cited
US4183134A
Cited
GB2005073A
Cited
GB2021346A
Cited
US4177084A
Cited
US4282556A
Cited
JPS5690549A
Cited
US4420743A
Cited
US4385937A
Cited
US4425700A
Cited
US4549198A
Cited
JPS57197848A
Cited
US4463492A
Cited
US4418470A
Cited
US4509990A
Cited
US4488230A
Cited
US4523963A
Cited
US4876582A
Cited
US5313077A
Cited
US4598305A
Cited
US4588447A
Cited
US4607176A
Cited
JPS61103530A
Cited
US4617066A
Cited
US4659392A
Cited
US4615762A
Cited
JPS62176145A
Cited
US4717836A
Cited
US4682055A
Cited
US4843442A
Cited
US4775641A
Cited
US4766482A
Cited
EP0273702A2
Cited
US4851721A
Cited
US5166767A
Cited
US5229644A
Cited
WO1989007367A2
Cited
US4872010A
Cited
US4843448A
Cited
US4989057A
Cited
US4907041A
Cited
US5141882A
Cited
US5066613A
Cited
US5027171A
Cited
US5170373A
Cited
US5196802A
Cited
JPH04122020A
Cited
US5294823A
Cited
US5242849A
Cited
JPH0555470A
Cited
US5145802A
Cited
US5391903A
Cited
EP0605946A2
Cited
EP0600596A2
Cited
US5300443A
Cited
US5341009A
Cited
WO1995002892A1
Cited
US5416043A
Cited
US5656524A
Cited
US5489547A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |