ESD protection for SOI circuits

Claim 2

An ESD protection device for use with semiconductor-on-insulator circuits, comprising: a semiconductor-on-insulator structure including a semiconductor material adapted for forming transistors therein; a conductor for carrying signals with respect to said transistor circuits; and a field effect transistor connected to said conductor for carrying ESD currents, said transistor having a semiconductor body defining a conduction channel between a semiconductor drain and a semiconductor source, said semiconductor body being electrically isolated from other semiconductor bodies formed from the semiconductor-on-insulator structure.

Claim 3

The ESD protection device of claim 1, wherein said transistor has one of said source or drain connected in common with a gate conductor of said transistor to define a two-terminal device.

Claim 4

The ESD protection device of claim 2, wherein said transistor exhibits a breakdown voltage characteristic having a reverse breakdown point and a holding voltage which is lower than said break point.

Claim 5

The ESD protection device of claim 3, wherein said transistor has a breakdown voltage characteristic which is a function of conduction channel length between said source and drain.

Claim 6

The ESD protection device of claim 3, wherein said breakdown point is about 12 volts, and said holding voltage is greater than about 7 volts.

Claim 7

The ESD protection device of claim 1, wherein said transistor comprise: an N-channel field effect transistor.

Claim 8

The ESD protection device of claim 1, further including a pair said transistors, each connected to said conductor, and further including a supply voltage conductor connected to one said transistor, and a ground conductor connected to the other said transistor.

Claim 9

The ESD protection device of claim 7, further including a pair of gated diode devices to provide a low forward voltage characteristic to an ESD protection circuit formed thereby.

Claim 10

The ESD protection device of claim 8, wherein said pair of transistors defines a primary protection circuit, and further including a second pair of said transistors connected in parallel to said primary protection circuit, and a resistor connecting said primary protection circuit to said second pair of transistors.

Claim 11

A transistor for providing ESD protection to a semiconductor-on-insulator circuit, comprising: a field effect transistor having a semiconductor body defining a conduction channel between a semiconductor source region and a semiconductor drain region, said semiconductor body being electrically isolated from other transistor semiconductor bodies of the semiconductor-on-insulator circuit means connecting together one of said source or drain regions to a gate conductor of said field effect transistor; and said transistor exhibiting an electrical characteristic having a reverse breakdown voltage and a holding voltage which is substantially lower than said breakdown voltage to thereby minimize power consumption of said field effect transistor.

Claim 12

A transistor for providing ESD protection to a semiconductor-on-insulator circuit, comprising: a field effect transistor having a semiconductor body defining a conduction channel between a semiconductor source region and a semiconductor drain region, said semiconductor body being electrically isolated from other transistor semiconductor bodies of the semiconductor-on-insulator circuit means connecting together one of said source or drain regions to a gate conductor of said field effect transistor; and said transistor exhibiting an electrical characteristic having a reverse breakdown voltage and a holding voltage which is substantially lower than said breakdown voltage to thereby minimize power consumption of said field effect transistor.

Claim 13

The transistor of claim 10, wherein said field effect transistor comprises an N-channel transistor.

Claim 14

The transistor of claim 10, wherein said transistor has a reverse breakdown voltage less than about 14 volts.

Claim 15

The transistor of claim 10, further including in combination a gated diode connected in parallel to said transistor, and wherein said transistor has a lower reverse breakdown voltage than that of said gated diode.

Claim 16

The transistor of claim 11, wherein said gated diode is characterized with a lower forward conducting voltage than that of said transistor.

Claim 17

The transistor of claim 10, wherein the semiconductor body of said transistor is adapted to change a characteristic voltage thereof in response to an accumulation of charge therein.

Claim 18

The transistor cf claim 13, wherein said transistor comprises a floating body device.

Claim 19

An electrostatic discharge protection circuit, comprising: a power supply bonding pad and an associated power supply bus; a ground bonding pad and an associated ground bus; a signal bonding pad and an associated signal bus; a first and second gated diode connected to said signal bus and respectively to said power supply bus and said ground bus; a first and second floating body transistor defining a primary protection circuit connected to said signal bus and respectively to said power supply bus and said ground bus; a first and second floating body transistor defining a secondary protection circuit connected to said signal bus and respectively to said power supply bus and said ground bus; and a resistor connecting said primary protection circuit to said secondary protection circuit.

Claim 20

An electrostatic discharge protection circuit, comprising: a power supply bonding pad and an associated power supply bus; a ground bonding pad and an associated ground bus; a signal bonding pad and an associated signal bus; a first and second gated diode connected to said signal bus and respectively to said power supply bus and said ground bus; a first and second floating body transistor defining a primary protection circuit connected to said signal bus and respectively to said power supply bus and said ground bus; a first and second floating body transistor defining a secondary protection circuit connected to said signal bus and respectively to said power supply bus and said ground bus; and a resistor connecting said primary protection circuit to said secondary protection circuit.

Claim 21

The circuit of claim 17, wherein said primary and secondary protection circuits comprise N-channel field effect transistors each having a breakdown voltage and a lower holding voltage.

Claim 22

The circuit of claim 17, wherein said primary and secondary protection circuits comprise field effect transistors each configured as a two-terminal device.

Claim 23

The circuit of claim 19, wherein said transistors each have a gate terminal connected to a source terminal.