Transistor process for removing narrow base effects

Claim 1

A process for fabricating NPN transistors in a silicon wafer comprising the steps: providing a silicon wafer having an N type region into which an NPN transistor is to be formed; forming a field oxide over said wafer except where said transistors are to be located; applying a first masking resist over said wafer having photolithographically created openings located over said wafer portions where said transistor emitter regions are to be located; applying an N type impurity inside the openings in said first masking resist and controlling the quantity of said N type impurity to provide the desired transistor emitter doping; applying a second masking resist over said wafer having photolithographically created openings located over wafer portions where said transistor base regions are to be located; applying a P type impurity inside the openings in said second masking resist and controlling the quantity of said P type impurity to provide the desired transistor base doping; and heating said wafer to activate and diffuse said P and N type impurities in said wafer; characterised by the step of: subjecting said wafer to an etch which attacks said oxide preferentially with respect to said silicon prior to the step of applying a P type impurity.