US3699544A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Three transistor memory cell
Assignee: General Electric Co
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Filing: 1971-05-26
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Granted: 1972-10-17
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Expires: 1991-05-26
Abstract
Abstract A three transistor dynamic memory cell is disclosed utilizing a voltage controlled capacitor to enhance signal coupling in the cell. In addition, the refreshing operation is greatly enhanced due to the configuration of the cell; viz. refreshing is achieved without an inverting amplifier, several cells can be refreshed simultaneously, and refreshing can occur while other operations are performed by the same cell.
Inventors
- 👤 Reuben E Joynson
- 👤 Joseph L Mundy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:41
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/402; G11C11/403; G11C11/405
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
134 words
An improved three transistor memory cell comprising: firSt and second pairs of access lines; first and second field effect transistors having their sourcedrain paths series connected across said first pair of access lines; the gate of said first transistor forming a storage node for storing information in the form of electric charge; the gate of said second transistor coupled to one of said second pair of access lines and controlled by signals thereon; a third field effect transistor, having its gate coupled to the other of said second pair of access lines and controlled by signals thereon, for coupling signals to said storage node; and a voltage variable capacitor, comprising a gate electrode and a drain electrode, for selectively coupling signals from one of said first pairs of access lines to said storage node.
Claim 2
Dependent Claim
134 words
An improved three transistor memory cell comprising: firSt and second pairs of access lines; first and second field effect transistors having their sourcedrain paths series connected across said first pair of access lines; the gate of said first transistor forming a storage node for storing information in the form of electric charge; the gate of said second transistor coupled to one of said second pair of access lines and controlled by signals thereon; a third field effect transistor, having its gate coupled to the other of said second pair of access lines and controlled by signals thereon, for coupling signals to said storage node; and a voltage variable capacitor, comprising a gate electrode and a drain electrode, for selectively coupling signals from one of said first pairs of access lines to said storage node.
Claim 3
Dependent Claim
26 words
An improved memory cell as set forth in claim 1 wherein the drain electrode of said voltage variable capacitor comprises the drain of said first transistor.
Claim 4
Dependent Claim
34 words
An improved memory cell as set forth in claim 2 wherein the source-drain path of said third transistor is coupled between said storage node and the other of said first pair of access lines.
Claim 5
Dependent Claim
34 words
An improved memory cell as set forth in claim 1, wherein the drain electrode of said voltage variable capacitor comprises a separate drain electrode connected to one of said first pair of access lines.
Claim 6
Dependent Claim
33 words
An improved memory cell as set forth in claim 4 wherein the source-drain path of said third transistor is connected between said storage node and the junction of said first and second transistors.
Claim 7
Dependent Claim
33 words
An improved memory cell as set forth in claim 5 and further comprising a diode connecting said series connected first and second transistors to said one of said first pair of access lines.
Claim 8
Dependent Claim
24 words
An improved memory cell as set forth in claim 6 wherein said diode comprises a transistor having its gate and drain electrodes connected together.
Claim 9
Dependent Claim
52 words
An improved memory cell a set forth in claim 5 and further comprising a diode series connected between the source-drain paths of said first and second transistors, and wherein the source-drain path of said third transistor is connected between said storage node and the junction of said second transistor and said diode.
Claim 10
Dependent Claim
24 words
An improved memory cell as set forth in claim 8 wherein said diode comprises a transistor having its gate and drain electrodes connected together.
References Cited (Backward Citations)
US3286189A
Cited
US3582909A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |