US3582909A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ratioless memory circuit using conditionally switched capacitor
Assignee: Boeing North American Inc
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Filing: 1969-03-07
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Granted: 1971-06-01
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Expires: 1989-03-07
Abstract
Abstract The memory circuit includes a capacitor which has its capacitance conditionally switched between a substrate and an input electrode as a function of the potential on its fixed plate. If a potential representing a logic one state is applied to the fixed plate during a write period of the memory cycle, the capacitance is switched to the input electrode. During a read period of the memory cycle, the potential on the fixed plate is boosted by an amount proportional to the potential applied to the input electrode of the capacitor. The potential on the fixed plate is used on the gate electrode of a field effect device to drive the output electrode to the potential appearing on the input electrode, assuming that the boosted potential of the fixed plate is at least one threshold greater than the potential applied to the input electrode. The output voltage represents the logic state of the stored information. If a logic zero state had been stored, the capacitance would have remained connected to the substrate so that the voltage on the input electrode of the capacitance would have had no effect on the circuit. The circuit uses a second capacitor, regenerated during each read cycle, to regenerate the charge on the conditionally switched capacitor as well as the charge on the inherent capacitance connected to the conditionally switched capacitor. As a result, a nonvolatile memory is provided.
Inventors
- 👤 Robert K Booher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:03
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C11/402; G11C11/403
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
103 words
A memory circuit having an output voltage level relatively independent of the resistance ratio between circuit elements and having a memory cycle, said circuit comprising, means for applying a potential to said circuit representing the logic state of information being stored, an input electrode, capacitor means including a fixed plate connected to said means for applying, said capacitor means including a second plate comprising an inversion layer formed in the substrate region subjacent said fixed plate, said inversion layer being formed as a function of the logic state of the information being stored for electrically connecting said second plate to the input electrode.
Claim 2
Dependent Claim
103 words
A memory circuit having an output voltage level relatively independent of the resistance ratio between circuit elements and having a memory cycle, said circuit comprising, means for applying a potential to said circuit representing the logic state of information being stored, an input electrode, capacitor means including a fixed plate connected to said means for applying, said capacitor means including a second plate comprising an inversion layer formed in the substrate region subjacent said fixed plate, said inversion layer being formed as a function of the logic state of the information being stored for electrically connecting said second plate to the input electrode.
Claim 3
Dependent Claim
47 words
The combination recited in claim 1 wherein said capacitance is switched to said input electrode when the information being stored has a logic one state and wherein said capacitance is connected to a reference potential when the state of the information being stored is a logic zero.
Claim 4
Dependent Claim
68 words
The combination recited in claim 1 including read clock signal means connected to said input electrode for increasing the potential on said fixed plate when information having a logic one state is being stored by said capacitor means, means including an output electrode for responding to the potential on said capacitor plate after the increase for driving the output electrode to a potential representing said logic one state.
Claim 5
Dependent Claim
43 words
The combination recited in claim 3 wherein said capacitor means includes means for isolating from said means responsive when a logic zero state is stored by said capacitor means and said means responsive is prevented from responding to said read clock signal means.
Claim 6
Dependent Claim
75 words
The combination recited in claim 4 wherein said means for applying a potential to said memory circuit includes a first field effect transistor having a control electrode responsive to a write clock signal means for connecting said fixed plate to said potential during a write interval of said memory cycle during which interval logic information is stored in said memory circuit whereby resistive divider action is not required when storing the information in said circuit.
Claim 7
Dependent Claim
69 words
The combination recited in claim 5 wherein said means responsive to the potential on said fixed plate after the increase, includes a second field effect transistor having its control electrode connected to said fixed plate, a first electrode connected to said read clock signal means, and a second electrode driven to the voltage level of said read clock signal by the potential on said fixed plate after the increase.
Claim 8
Dependent Claim
76 words
The combination recited in claim 6 including a third field effect transistor having a first electrode connected to said second electrode of said second field effect transistor and having a control electrode connected to said read clock signal means for driving its second electrode to an output voltage representing a stored logic one state during a read interval of said memory cycle whereby resistive divider action is not required when reading out information from said circuit.
Claim 9
Dependent Claim
75 words
The combination recited in claim 6 including a third field effect transistor having a first electrode connected to said read clock signal means and having its control electrode connected to said seCond electrode of the second field effect transistor for driving its other electrode to a potential representing a stored logic one state during a read interval of said memory cycle whereby resistive divider action is not required when reading out information from said circuit.
Claim 10
Dependent Claim
30 words
The combination recited in claim 5 including means for providing sinusoidal read and write clock signals for avoiding the requirement of clock signals having relatively fast rise and fall times.
Claim 11
Dependent Claim
122 words
The combination recited in claim 7 including means for addressing said circuit and a capacitor means connected between said other electrode of the third field effect transistor and a reference potential for being charged to a potential representing the state of the stored logic information during said write interval of the memory cycle when said circuit is being addressed and for being regenerated by the potential of the voltage appearing on said second electrode of the third field effect transistor during the read interval of said memory cycle when the circuit is not being addressed, said capacitor being connected to said fixed plate during said write interval when the circuit is not being addressed for regenerating the charge of said capacitor means.
Claim 12
Dependent Claim
26 words
The combination recited in claim 10 including means for resetting the inherent capacitance of said means for addressing to a reference potential after every write interval.
Claim 13
Dependent Claim
121 words
The combination recited in claim 8 including means addressing said circuit and a capacitor means connected between said second electrode of the third field effect transistor and a reference potential for being charged to a potential representing the state of the stored logic information during said write interval of the memory cycle when said circuit is being addressed and for being regenerated by the potential of the voltage appearing on said second electrode of the third field effect transistor during the read interval of said memory cycle when the circuit is not being addressed, said capacitor being connected to said fixed plate during said write interval when the circuit is not being addressed for regenerating the charge of said capacitor means.
Claim 14
Dependent Claim
119 words
A field effect transistor ratioless memory circuit having a memory cycle, said circuit comprising, means including field effect transistor means for applying a potential to said circuit representing the logic state of information being stored, an input electrode, capacitor means including a field effect transistor and having a fixed plate connected to said means for applying and an inversion layer in a substrate region subjacent said fixed plate forming the second plate of said capacitor means, said inversion layer being formed by a voltage level on said fixed plate representing a certain logic state for switching the capacitance of said capacitor means conditionally to said input electrode as a function of the logic state of the information being stored.
Claim 15
Dependent Claim
119 words
A field effect transistor ratioless memory circuit having a memory cycle, said circuit comprising, means including field effect transistor means for applying a potential to said circuit representing the logic state of information being stored, an input electrode, capacitor means including a field effect transistor and having a fixed plate connected to said means for applying and an inversion layer in a substrate region subjacent said fixed plate forming the second plate of said capacitor means, said inversion layer being formed by a voltage level on said fixed plate representing a certain logic state for switching the capacitance of said capacitor means conditionally to said input electrode as a function of the logic state of the information being stored.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |