Thin-film integrated injection logic

Claim 2

An integrated injection logic semiconductor device comprising: an insulating substrate; a thin film of semiconductor material disposed over said insulating substrate; a lateral transistor having a base, an emitter and a collector region formed in said thin film of semiconductor material; a vertical transistor having a base, an emitter and a collector region, formed in said thin film of semiconductor material adjacent said load lateral transistor, said base region of said vertical transistor coinciding with said collector region of said lateral transistor.

Claim 3

The integrated injection logic semiconductor device of claim 1 wherein: said emitter region of said vertical transistor is located at a non-insulated surface of said semiconductor material.

Claim 4

the device of claim 2 wherein: said vertical transistor is an NPN transistor; and said lateral transistor is a PNP transistor.

Claim 5

The device of claim 1 wherein: said vertical transistor is an NPN transistor, and said lateral transistor is a PNP transistor.

Claim 6

The device of claim 1 wherein: said vertical transistor is a PNP transistor; and said lateral transistor is an NPN transistor.

Claim 7

The device of claim 2 wherein: said vertical transistor is a PNP transistor; and said lateral transistor is an NPN transistor.

Claim 8

The device of claim 1 wherein: said semiconductor material is silicon.

Claim 9

The device of claim 7 wherein: said insulating substrate is sapphire.

Claim 10

The device of claim 7 wherein: said insulating substrate is silicon dioxide.

Claim 11

An integrated injection logic semiconductor device comprising: an insulating substrate; a first region of a semiconductor of a first conductivity type position on said insulating substrate; a second region of said semiconductor of the opposite conductivity type positioned on said insulating substrate in contact with said first region so as to form a first lateral semiconductor junction therewith; a third region of said semiconductor of said first conductivity type having a portion thereof positioned on said substrate, in contact with said second region so as to form a second lateral semiconductor junction therewith; a fourth region of said semiconductor of said opposite conductivity type, encompassed by and on top of said third region, so as to form a first vertical semiconductor junction therewith; and a fifth region of said semiconductor of said opposite conductivity type positioned on said insulating substrate, in contact with and at least partially underlying said third region so as to form a second vertical semiconductor junction therewith.

Claim 12

An integrated injection logic semiconductor device comprising: an insulating substrate; a first region of a semiconductor of a first conductivity type position on said insulating substrate; a second region of said semiconductor of the opposite conductivity type positioned on said insulating substrate in contact with said first region so as to form a first lateral semiconductor junction therewith; a third region of said semiconductor of said first conductivity type having a portion thereof positioned on said substrate, in contact with said second region so as to form a second lateral semiconductor junction therewith; a fourth region of said semiconductor of said opposite conductivity type, encompassed by and on top of said third region, so as to form a first vertical semiconductor junction therewith; and a fifth region of said semiconductor of said opposite conductivity type positioned on said insulating substrate, in contact with and at least partially underlying said third region so as to form a second vertical semiconductor junction therewith.

Claim 13

The device of claim 10 further comprising: a passivating layer covering said semiconductor.

Claim 14

The device of claim 11 wherein said passivating layer is silicon dioxide.

Claim 15

The device of claim 11 further comprising: a first metal contact extending through said passivating layer and in contact with said first region; a second metal contact extending through said passivating layer and in contact with said second and forth regions; a third metal contact extending through said passivating layer and in contact with said third region; and at least one metal contact extending through said passivating layer and in contact with said fifth region.

Claim 16

The device of claim 13 wherein there are a plurality of metal contacts extending through said passivating layer and in contact with said fifth region.

Claim 17

The device of claim 14 wherein: said plurality of metal conducts are Schottky-barrier contacts.

Claim 18

The device of claim 13 wherein: said at least one metal contact is a Schottky-barrier contact.

Claim 19

The device of claim 10 wherein: said first conductivity type is p-type material and said second conductivity type is n-type material.

Claim 20

The device of claim 17 wherein: said first region is heavily doped p-type material.

Claim 21

The device of claim 18 wherein: said fourth region is heavily doped n-type material.

Claim 22

The device of claim 10 wherein: said first conductivity type is n-type material and said opposite conductivity type is p-type material.

Claim 23

The device of claim 20 wherein: said first region is heavily doped n-type material and said second region is heavily doped p-type material.

Claim 24

In an integrated injection logic semiconductor including a lateral transistor and an adjacent vertical transistor formed in a layer of semiconductor material, the improvement wherein: said layer of semiconductor material is formed directly on the surface of an insulating substrate.

Claim 25

In an integrated injection logic semiconductor including a lateral transistor and an adjacent vertical transistor formed in a layer of semiconductor material, the improvement wherein: said layer of semiconductor material is formed directly on the surface of an insulating substrate.

Claim 26

The improvement of claim 11 wherein: said vertical transistor has a base, a collector and an emitter and wherein said emitter is at a non-insulated surface of said semiconductor material.

Claim 27

In an integrated injection logic semiconductor including a lateral transistor and an adjacent vertical transistor formed in a layer of semiconductor material, said vertical transistor having a base, a collector and an emitter, the improvement wherein: said emitter is at a non-insulated surface of said semiconductor material.

Claim 28

In an integrated injection logic semiconductor including a lateral transistor and an adjacent vertical transistor formed in a layer of semiconductor material, said vertical transistor having a base, a collector and an emitter, the improvement wherein: said emitter is at a non-insulated surface of said semiconductor material.