Gallium arsenide ISL gate with punched-through bipolar driver transistor

Claim 1

A gallium arsenide static induction transistor integrated circuit formed in a semiconductor body comprising: a semi-insulating substrate; an epitaxial layer grown on said semi-insulting substrate; a static induction transistor; and a resistor connected as a load of said static induction transistor, and resistor and said static induction transistor being formed on said epitaxial layer; wherein said static induction transistor comprises an n + source region formed in contact with a main surface of said epitaxial layer; a p + gate region formed in contact with said main surface of said epitaxial layer with said gate region substantially surrounding said source region; an n + buried drain region adjacent to said semi-insulating substrate; a low impurity concentration current path region substantially surrounded by said source, gate and drain regions, said current path region including a low impurity p region adjacent to at least said source region, said current path region having dimensions and impurity concentrations so as to be completely covered with a depletion region at a zero, off-state gate bias; and at least one Schottky contact connected as an output terminal to said drain region; and wherein said resistor comprises a p region formed in contact with said main surface of said epitaxial region; and at least a semi-insulating region between said p region and said semi-insulating substrate.