Semiconductor integrated circuit device containing lateral and planar transistor in a semiconductor layer

Abstract

Abstract A SEMICONDUCTOR DEVICE HAVING A STRUCTURE WHEREIN, BY DIFFUSING AN N-TYPE IMPURITY IN A P-TYPE SEMICONDUCTOR SUBSTRATE, AN N-TYPE SEMICONDUCTOR LAYER WHICH COMPRISES AN ISOLATED SEMICONDUCTOR BULK REGION, IS FORMED ON ONE OF THE SURFACES OF THE SUBSTRATE AND IS ELECTRICALLY ISOLATED FROM SAID SUBSTRATE. BY DIFFUSING A P-TYPE IMPURITY AT THREE POSITIONS IN SAID N-TYPE SEMICONDUCTIVE LAYER, FIRST, SECOND AND THIRD P-TYPE REGIONS THAT ARE LATERALLY INTERLAID ARE FORMED. BY DIFFUSING AN N-TYPE IMPURITY INTO THE SURFACE OF THE THIRD P-TYPE REGION, A FOURTH N-TYPE REGION IS FORMED. AS A RESULT OF THIS ARRANGEMENT, A PNPTYPE LATERAL TRANSISTOR IN WHICH SAID FIRST P-TYPE REGION, SAID SECOND P-TYPE REGION AND SAID N-TYPE SEMICONDUCTIVE LAYER SERVE AS AN EMITTER, A COLLECTOR AND A BASE, RESPECTIVELY; AND A NPN-TYPE DOUBLE DIFFUSED PLANAR TRANSISTOR IN WHICH SAID THIRD P-TYPE REGION, SAID FOURTH N-TYPE REGION AND SAID N-TYP SEMICONDUCTIVE LAYER SERVE AS A BASE, AN EMITTER AND A COLLECTOR, RESPECTIVELY, ARE OBTAINED IN THE BULK REGION PROVIDED BY THE SEMICONDUCTIVE LAYER AND, FURTHERMORE, THE BASE OF THE LATERAL TRANSISTOR IS ELECTRICALLY CONNECTED INTERNALLY TO THE COLLECTOR OF THE PLANAR TRANSISTOR THROUGH THE BULK REGION PROVIDED BY THE SEMICONDUCTIVE LAYER.

Inventors

• 👤 Minoru Nagata

Bibliographic Details