US4076556A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabrication of improved bipolar injection logic circuit
Assignee: AT&T Inc
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Filing: 1976-06-01
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Granted: 1978-02-28
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Expires: 1996-06-01
Abstract
Abstract An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.
Inventors
- 👤 Jorge Agraz-Guerena
- 👤 Alan William Fulton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:38
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/63; H10D84/611; H10D84/65; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/085; Y10S148/087
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
151 words
A method of manufacture of integrated semiconductor devices comprising the following steps which are performed in the stated order on a chip which comprises an epitaxial layer of one conductivity type overlying a substrate of the same conductivity type and having higher conductivity than said epitaxial layer: a. By diffusion forming in the epitaxial layer a region of the opposite conductivity type extending through the epitaxial layer to the substrate and shaped to encircle a selected region of the epitaxial layer; b. Implanting within said selected region a region of the said opposite conductivity type between, but spaced apart from, the surfaces of said epitaxial layer and extending only to said encircling region thereby forming in each encircled region a vertical three-element semiconductor device; c. Forming for each encircled region a corresponding metallized contact at the exposed surface of the epitaxial layer and overlying a part of the corresponding encircled region.
Claim 2
Independent Claim
151 words
A method of manufacture of integrated semiconductor devices comprising the following steps which are performed in the stated order on a chip which comprises an epitaxial layer of one conductivity type overlying a substrate of the same conductivity type and having higher conductivity than said epitaxial layer: a. By diffusion forming in the epitaxial layer a region of the opposite conductivity type extending through the epitaxial layer to the substrate and shaped to encircle a selected region of the epitaxial layer; b. Implanting within said selected region a region of the said opposite conductivity type between, but spaced apart from, the surfaces of said epitaxial layer and extending only to said encircling region thereby forming in each encircled region a vertical three-element semiconductor device; c. Forming for each encircled region a corresponding metallized contact at the exposed surface of the epitaxial layer and overlying a part of the corresponding encircled region.
Claim 3
Dependent Claim
58 words
The method according to claim 1 comprising the following additional step: d. By diffusion forming in the epitaxial layer a further region of the said opposite conductivity type extending through the epitaxial layer to the substrate and spaced apart from the through-extending region of the same conductivity type, thereby forming a lateral transistor circuit in said epitaxial layer.
Claim 4
Dependent Claim
48 words
The method in accordance with claim 2 further comprising the following step: e. By diffusion forming at the surface of said epitaxial layer in the area separating said through-extending regions of the said opposite conductivity type a region of the first conductivity type having an excess of impurity.
Claim 5
Independent Claim
123 words
A method of manufacture of integrated semiconductor devices comprising the following steps which are performed in the following order on a chip which comprises an N-type epitaxial layer overlying an N+ substrate: a. By diffusion forming in the epitaxial layer a P-type region extending through the epitaxial layer to the substrate and shaped to encircle a selected region of the epitaxial layer; b. Implanting a P-type region between, but spaced apart from, the surfaces of said epitaxial layer and extending only to said encircling region, thereby forming in each encircled region a vertical NPN semiconductor device; c. Forming for each encircled region a corresponding metallized contact at the exposed surface of the epitaxial layer and overlying a part of the corresponding encircled region.
Claim 6
Independent Claim
123 words
A method of manufacture of integrated semiconductor devices comprising the following steps which are performed in the following order on a chip which comprises an N-type epitaxial layer overlying an N+ substrate: a. By diffusion forming in the epitaxial layer a P-type region extending through the epitaxial layer to the substrate and shaped to encircle a selected region of the epitaxial layer; b. Implanting a P-type region between, but spaced apart from, the surfaces of said epitaxial layer and extending only to said encircling region, thereby forming in each encircled region a vertical NPN semiconductor device; c. Forming for each encircled region a corresponding metallized contact at the exposed surface of the epitaxial layer and overlying a part of the corresponding encircled region.
Claim 7
Dependent Claim
52 words
The method according to claim 4 comprising the following additional step: d. By diffusion forming in the epitaxial layer a further P-type region extending through the epitaxial layer to the substrate and spaced apart from the through-extending P-type impurity region, thereby forming a lateral current source transistor circuit in said epitaxial layer.
Claim 8
Dependent Claim
36 words
A method in accordance with claim 5 further comprising the following step: e. By diffusion forming an N+ impurity region at the surface of said epitaxial layer in the area separating said through-extending P-type impurity regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-27 | 1981-08-29 | 1982-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-27 | 1985-08-29 | 1986-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-27 | 1989-08-29 | 1990-02-28 | $7700.00 | Window Closed / Lapsed |