Method for memorizing a data bit in an integrated mos-type static random access memory cell, a transistor for performing the method, and and the memory so obtained

Claim 2

A metal-oxide-semiconductor field effect transistor (MOSFET) (12) comprising a semiconductor substrate (11), a source region (13a) and a drain region (14a) incorporated in said semiconductor substrate, said source region and said drain region being respectively connected to source and drain potentials (Vs, Vd) and delimiting a doped channel (19) therebetween, and a gate 15a) overlying said channel (19) through a gate oxide layer (18) and being connected to a gate potential (Vg), said transistor having a subthreshold conduction condition in which a drain-source current (IDs) shows a hysteresis cycle when one of said drain potential or gate potential is varied up and down.

Claim 3

A transistor as defined in claim 1, wherein the doped channel (19) has a predetermined low concentration of dopants sufficient to make the hysteresis cycle in the drain-source current (Ids) distinguishable from current limited by space charge in the channel.

Claim 4

A transistor as defined in claim 1, wherein said transistor comprises a short-channel type MOSFET, and said gate (15a) has a length, measured in a direction of said drain-source current, which is less than approximately 5 micrometers.

Claim 5

An integrated metal-oxide-semiconductor (MOS)-type static random access memory (RAM) (10) including a semiconductor substrate (11) and at least one memory cell (21) comprising a memory metal-oxide-semiconductor field effect transistor (MOSFET) (12) having, in said semiconductor substrate, a source region (13a) and a drain region (14a) respectively connected to source and drain potentials (Vs, Vd) and delimiting a doped channel (19) therebetween, and, over said semiconductor substrate, a gate (15a) operatively overlying said channel through a gate oxide layer (18) and being connected to a gate potential (Vg), said memory MOSFET having a subthreshold conduction condition in which a drain-source current (Ids) shows a hysteresis cycle when one of said drain potential or gate potential is varied up and down; and means for writing (23) and means for reading (24) data in said memory MOSFET.

Claim 6

An integrated metal-oxide-semiconductor (MOS)-type static random access memory (RAM) (10) including a semiconductor substrate (11) and at least one memory cell (21) comprising a memory metal-oxide-semiconductor field effect transistor (MOSFET) (12) having, in said semiconductor substrate, a source region (13a) and a drain region (14a) respectively connected to source and drain potentials (Vs, Vd) and delimiting a doped channel (19) therebetween, and, over said semiconductor substrate, a gate (15a) operatively overlying said channel through a gate oxide layer (18) and being connected to a gate potential (Vg), said memory MOSFET having a subthreshold conduction condition in which a drain-source current (Ids) shows a hysteresis cycle when one of said drain potential or gate potential is varied up and down; and means for writing (23) and means for reading (24) data in said memory MOSFET.

Claim 7

An integrated MOS-type static random access memory as defined in claim 4, wherein said channel has a predetermined low concentration of dopants sufficient to make the hysteresis cycle in the drain-source current (Ids) distinguishable from current limited by a space charge in the channel.

Claim 8

An integrated MOS-type static random access memory as defined in claim 4, wherein the memory MOSFET is of the short-channel type.

Claim 9

An integrated MOS-type static random access memory as defined in claim 4, wherein said writing means (23) comprises a first MOSFET (23a) having a drain-source path serially connected with said memory MOSFET (12) to a first writing wire (Wr) and having a gate electrode connected to a second writing wire (Wc).

Claim 10

An integrated MOS-type static random access memory as defined in claim 7, wherein said first MOSFET is of a depletion type.

Claim 11

An integrated MOS-type static random access memory as defined in claim 7, wherein said cell further comprises addressing means, said addressing means including said first MOSFET.

Claim 12

An integrated MOS-type static random access memory as defined in claim 4, wherein said reading means (24) comprises a second MOSFET (24a) having a drain-source path serially connected with said memory MOSFET to a first reading wire (Rr) and having a gate electrode connected to a second reading wire (Rc).

Claim 13

An integrated MOS-type static random access memory as defined in claim 10, wherein said first reading wire (Rr) has a high capacitance, and said cell further comprises means (24b) for discharging said capacitance.

Claim 14

An integrated MOS-type static random access memory as defined in claim 11, wherein said discharging means comprises a third MOSFET (24b) having a drain-gate serially connected with the drain-source path of said second MOSFET (24a) to said reading wire (Rr).

Claim 15

A short-channel type metal-oxide-semiconductor field effect transistor (12) comprising a semiconductor substrate (11), a source region (13a) and a drain region (14a) incorporated in said semiconductor substrate and respectively connected to source and drain poatentials (Vs, Vd) and delimiting a channel (19) therebetween having a predetermined low concentration of dopants, and a gate (15a) overlying said channel (19) and a gate oxide layer (18), the gate being connected to a gate potential (Vg), said transistor having a subthreshold conduction condition in which drain-source current (Ids) shows a hysteresis cycle when one of said drain potential or gate potential is varied up and down.

Claim 16

A short-channel type metal-oxide-semiconductor field effect transistor (12) comprising a semiconductor substrate (11), a source region (13a) and a drain region (14a) incorporated in said semiconductor substrate and respectively connected to source and drain poatentials (Vs, Vd) and delimiting a channel (19) therebetween having a predetermined low concentration of dopants, and a gate (15a) overlying said channel (19) and a gate oxide layer (18), the gate being connected to a gate potential (Vg), said transistor having a subthreshold conduction condition in which drain-source current (Ids) shows a hysteresis cycle when one of said drain potential or gate potential is varied up and down.