US4872010A
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Analog-to-digital converter made with focused ion beam technology
Assignee: The AT&T MVPD Group LLC
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Filing: 1988-02-08
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Granted: 1989-10-03
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Expires: 2008-02-08
Abstract
Abstract An analog-to-digital converter 10 employs a series of comparators 12, 14, 16 and 18. Each comparator includes at least one inverter consisting of a CMOS transistor pair including a P-channel transistor 22 and N-channel transistor 24. The threshold levels of the transistors 22, 24 are modified using focused ion beam implantation techniques to provide the comparators with monotonically increasing transistion levels.
Inventors
- 👤 Lawrence E. Larson
- 👤 Joseph F. Jensen
- 👤 Robert H. Walden
- 👤 Adele E. Schmitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:39
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/36; H10; H10D; H10D30/00; H10D30/60; H10D30/637; H03M1/361; H10D30/67; H10D30/6704; H10D30/6708; H10D30/6758; H10D30/6759; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D86/00; H10D30/6757
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
147 words
An analog-to-digital (A/D) converter comprising: a plurality of comparators having monotonically increasing transition levels, each comparator including at least one field effect transistor having drain, source and gate regions; the gate region overlying a channel in a semiconductor substrate; input means for providing an analog input signal simultaneously to each comparator; the transistors in each comparator each having a different threshold level due to different concentrations of impurities implanted in the channel regions thereof by focused ion beam implantation techniques thereby defining said transition levels for each of the comparators; and decoder means coupled to outputs of each of the comparators for generating a digital output signal as a function of the comparator outputs; each comparator including a least one complementary metal oxide (CMOS) inverter employing an N-channel and P-channel transistor; each comparator comprising a pair of cross coupled inverters adapted to receive differential analog input signals.
Claim 2
Dependent Claim
147 words
An analog-to-digital (A/D) converter comprising: a plurality of comparators having monotonically increasing transition levels, each comparator including at least one field effect transistor having drain, source and gate regions; the gate region overlying a channel in a semiconductor substrate; input means for providing an analog input signal simultaneously to each comparator; the transistors in each comparator each having a different threshold level due to different concentrations of impurities implanted in the channel regions thereof by focused ion beam implantation techniques thereby defining said transition levels for each of the comparators; and decoder means coupled to outputs of each of the comparators for generating a digital output signal as a function of the comparator outputs; each comparator including a least one complementary metal oxide (CMOS) inverter employing an N-channel and P-channel transistor; each comparator comprising a pair of cross coupled inverters adapted to receive differential analog input signals.
Claim 3
Dependent Claim
17 words
The converter of claim 1 wherein outputs of each inverter are coupled directly to said decoder means.
Claim 4
Dependent Claim
93 words
An integrated circuit device comprising: a digital device having at least one transistor with a given threshold level; a plurality of analog device comparators having monotonically increasing transition levels, each comparator including at least one field effect transistor having drain, source and gate regions; the gate regions overlying a channel in said semiconductor substrate; said channels in each transistor having different concentrations of impurities therein implanted by focused ion beam implantation techniques thereby defining monotonically different transition levels for the comparators; said digital and analog devices being formed on the same semiconductor substrate.
Claim 5
Dependent Claim
93 words
An integrated circuit device comprising: a digital device having at least one transistor with a given threshold level; a plurality of analog device comparators having monotonically increasing transition levels, each comparator including at least one field effect transistor having drain, source and gate regions; the gate regions overlying a channel in said semiconductor substrate; said channels in each transistor having different concentrations of impurities therein implanted by focused ion beam implantation techniques thereby defining monotonically different transition levels for the comparators; said digital and analog devices being formed on the same semiconductor substrate.
Claim 6
Dependent Claim
13 words
The device of claim 3 which includes metallic alignment targets adjacent the transistors.
Claim 7
Dependent Claim
48 words
The device of claim 3 wherein each comparator includes at least one inverter having a CMOS transistor pair having a P-channel and N-channel transistor, the impurity concentration in the gate regions of the N-channel and P-channel transistors being different thereby providing each comparator with a different transition level.
Claim 8
Dependent Claim
74 words
The device of claim 5 wherein said digital device includes at least one CMOS transistor pair having an N-channel and P-channel transistor, with the impurity concentration in the channel regions of the N-channel transistors of the digital device being different than the N-channel transistors in the analog device, and wherein the channel regions in the P-channel transistors of the digital device have different impurity concentration levels than the P-channel transistors of the analog device.
Claim 9
Dependent Claim
21 words
The device of claim 6 wherein said analog and digital device are formed in silicon mesas supported by a sapphire base.
Claim 10
Dependent Claim
47 words
The device of claim 7 wherein the source region of at least one transistor in the analog device has two regions of one type impurity separated by an island of another type impurity which is connected to and is of the same type as the gate region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |