Regrowing selectively formed ion amorphosized regions by thermal gradient

Claim 1

A method for manufacturing a semiconductor device having a semiconductive layer such as a silicon layer on a substrate made of electrically insulative material such as sapphire, which comprises the steps of: (a) forming a layer of single-crystalline semiconductive material such as silicon on a surface, which is defined by a first crystal plane, or said substrate having a first thermal expansion rate, said layer having a second thermal expansion rate and a second crystal plane as its principal plane; (b) injecting selected ions into said layer to partially convert the single-crystalline semiconductive material into a first layer region which is a amorphous semiconductive material and a second region which remains a single-crytalline semiconductive material, said first layer region being positioned below said second layer region and being substantially in contact with said substrate, and said second layer region including a surface of said layer and having a predetermined thickness; (c) annealing a structure obtained through the preceding steps to reconvert said amorphous material of said first layer region to single-crystalline semiconductive material on the basis of solid phase growth with said second layer region as a seed, while keeping said first and second layer regions of said layer at a first temperature and at least a large part of said substrate at a second temperature lower than said first temperature, so as to finally form a single-crystalline semiconductive layer on said substrate, whereby, when said annealed structure returns to room temperature, said single-crystalline semiconductive layer is prevented from having therein a compressive stress due to thermal contraction of said substrate.

Claim 2

A method for manufacturing a semiconductor device having a semiconductive layer such as a silicon layer on a substrate made of electrically insulative material such as sapphire, which comprises the steps of: (a) forming a layer of single-crystalline semiconductive material such as silicon on a surface, which is defined by a first crystal plane, or said substrate having a first thermal expansion rate, said layer having a second thermal expansion rate and a second crystal plane as its principal plane; (b) injecting selected ions into said layer to partially convert the single-crystalline semiconductive material into a first layer region which is a amorphous semiconductive material and a second region which remains a single-crytalline semiconductive material, said first layer region being positioned below said second layer region and being substantially in contact with said substrate, and said second layer region including a surface of said layer and having a predetermined thickness; (c) annealing a structure obtained through the preceding steps to reconvert said amorphous material of said first layer region to single-crystalline semiconductive material on the basis of solid phase growth with said second layer region as a seed, while keeping said first and second layer regions of said layer at a first temperature and at least a large part of said substrate at a second temperature lower than said first temperature, so as to finally form a single-crystalline semiconductive layer on said substrate, whereby, when said annealed structure returns to room temperature, said single-crystalline semiconductive layer is prevented from having therein a compressive stress due to thermal contraction of said substrate.

Claim 10

A method for manufacturing a semiconductor device having a silicon layer on a sapphire substrate, which comprises the steps of: (a) forming a layer of single-crystalline silicon on a surface of said substrate having a first thermal expansion rate, said layer having a surface and a second thermal expansion rate, and said substrate surface including first and second surface areas adjacent to each other; (b) converting a first portion of said single-crystalline silicon layer, positioned on the first surface area of said substrate, into a first layer region which is amorphous silicon and a second layer region which remains single-crystalline silicon, said first layer region being positioned below said second layer region and said second layer region including the surface of said layer and having a predetermined thickness; (c) converting a second portion of said single-crystalline silicon of another layer section, position on the second surface area of said substrate, into a third layer region which is amorphous silicon and a fourth layer region which remains single-crystalline silicon, said third layer region including the surface of said layer and having a predetermined thickness and said fourth layer region being positioned below said third layer region; (d) annealing a structure obtained through the preceding steps to reconvert said first and third layer regions of amorphous silicon into single-crystalline regions on the basis of solid state growth with single-crystalline silicon of each of said second and fourth layer regions as a seed, while keeping said silicon layer at a first temperature and at least a large part of said sapphire substrate at a second temperature lower than said first temperature, so as to finally form a first and second single-crystalline silicon layers which are adjacent to each other on said substrate; and (e) forming on said first single-crystalline silicon layer at least one first active semiconductor element which functions by substantially using as the majority carrier thereof and forming on said single-crystalline silicon layer at least one second active semiconductor element which functions by substantially using holes as the majority carrier thereof.

Claim 11

A method for manufacturing a semiconductor device having a silicon layer on a sapphire substrate, which comprises the steps of: (a) forming a layer of single-crystalline silicon on a surface of said substrate having a first thermal expansion rate, said layer having a surface and a second thermal expansion rate, and said substrate surface including first and second surface areas adjacent to each other; (b) converting a first portion of said single-crystalline silicon layer, positioned on the first surface area of said substrate, into a first layer region which is amorphous silicon and a second layer region which remains single-crystalline silicon, said first layer region being positioned below said second layer region and said second layer region including the surface of said layer and having a predetermined thickness; (c) converting a second portion of said single-crystalline silicon of another layer section, position on the second surface area of said substrate, into a third layer region which is amorphous silicon and a fourth layer region which remains single-crystalline silicon, said third layer region including the surface of said layer and having a predetermined thickness and said fourth layer region being positioned below said third layer region; (d) annealing a structure obtained through the preceding steps to reconvert said first and third layer regions of amorphous silicon into single-crystalline regions on the basis of solid state growth with single-crystalline silicon of each of said second and fourth layer regions as a seed, while keeping said silicon layer at a first temperature and at least a large part of said sapphire substrate at a second temperature lower than said first temperature, so as to finally form a first and second single-crystalline silicon layers which are adjacent to each other on said substrate; and (e) forming on said first single-crystalline silicon layer at least one first active semiconductor element which functions by substantially using as the majority carrier thereof and forming on said single-crystalline silicon layer at least one second active semiconductor element which functions by substantially using holes as the majority carrier thereof.