Patent US5843799A successfully refreshed from Google Patents.
US5843799A
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Circuit module redundancy architecture process
Assignee: Peraso Inc
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Filing: 1997-01-13
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Granted: 1998-12-01
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Expires: 2017-01-13
Abstract
Abstract A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.
Inventors
- 👤 Fu-Chieh Hsu
- 👤 Wingyu Leung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:47
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/83; G11C29/832; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/202; G06F11/2051; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/4077; G11C29/006; G11C29/04; G11C29/08; G11C29/48; G11C29/76; G11C29/80; G11C29/808; G11C29/88; H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G06F11/2023; G06F11/2028; H10D; H10D89/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
176 words
A method for forming a first semiconductor device having a first size and a second semiconductor device having a second smaller size using a single mask set, the method comprising the steps of: forming a plurality of circuit blocks on a semiconductor substrate, each circuit block of said plurality of circuit blocks comprising a plurality of replaceable circuit modules; forming programmable interconnect circuitry extending to each of the circuit modules, wherein the circuit blocks and the interconnect circuitry are fabricated from the single mask set; testing to determine whether the replaceable circuit modules are defective or functional; disconnecting a first set of the replaceable circuit modules from the interconnect circuitry; connecting a second set of the replaceable circuit modules to the interconnect circuitry, the second set comprising functional circuit modules; and selecting the number of circuit modules in the second set to correspond to the first size to form the first semiconductor device, or selecting the number of circuit modules in the second set to correspond to the second size to form the second semiconductor device.
Claim 2
Independent Claim
176 words
A method for forming a first semiconductor device having a first size and a second semiconductor device having a second smaller size using a single mask set, the method comprising the steps of: forming a plurality of circuit blocks on a semiconductor substrate, each circuit block of said plurality of circuit blocks comprising a plurality of replaceable circuit modules; forming programmable interconnect circuitry extending to each of the circuit modules, wherein the circuit blocks and the interconnect circuitry are fabricated from the single mask set; testing to determine whether the replaceable circuit modules are defective or functional; disconnecting a first set of the replaceable circuit modules from the interconnect circuitry; connecting a second set of the replaceable circuit modules to the interconnect circuitry, the second set comprising functional circuit modules; and selecting the number of circuit modules in the second set to correspond to the first size to form the first semiconductor device, or selecting the number of circuit modules in the second set to correspond to the second size to form the second semiconductor device.
Claim 3
Dependent Claim
44 words
The method of claim 1, further comprising the steps of: forming an input/output (I/O) port on the substrate; and forming at least one transceiver on the substrate, wherein the transceiver is located along the interconnect circuitry between the circuit modules and the I/O port.
Claim 4
Dependent Claim
33 words
The method of claim 1, further comprising the step of forming at least one transceiver on the substrate, wherein the transceiver is located along the interconnect circuitry between two of the circuit blocks.
Claim 5
Dependent Claim
21 words
The method of claim 3, further comprising the step of providing tri-state control signals to control the operation of the transceiver.
Claim 6
Dependent Claim
18 words
The method of claim 1, further comprising the step of locating the circuit blocks in a grid pattern.
Claim 7
Dependent Claim
21 words
The method of claim 1, further comprising the step of forming said each circuit block to be approximately the same size.
Claim 8
Dependent Claim
19 words
The method of claim 1, wherein the first set of replaceable circuit modules comprises the defective replaceable circuit modules.
Claim 9
Dependent Claim
23 words
The method of claim 7, wherein the first set of replaceable circuit modules further comprises one or more of said functional circuit modules.
Claim 10
Dependent Claim
25 words
The method of claim 1, wherein the first size is that of a full wafer and the second size is that of a fractional wafer.
Claim 11
Dependent Claim
20 words
The method of claim 9, wherein the fractional wafer size includes one or more of said plurality of circuit blocks.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-30 | 2002-06-01 | 2002-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-30 | 2006-06-01 | 2006-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-30 | 2010-06-01 | 2010-12-01 | $7700.00 | Window Closed / Lapsed |