Patent US5744980A successfully refreshed from Google Patents.
US5744980A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flexible, high-performance static RAM architecture for field-programmable gate arrays
Assignee: Microsemi SoC Corp
•
Filing: 1996-02-16
•
Granted: 1998-04-28
•
Expires: 2016-02-16
Abstract
Abstract A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof. Each of the random access memory blocks has address inputs, control inputs, data inputs, and data outputs. User-programmable interconnect elements are connected between the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks and selected ones of the interconnect conductors in the horizontal routing channels passing therethrough. Programming circuitry is provided for programming selected ones of the user-programmable interconnect conductors to connect the inputs and outputs of the logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks.
Inventors
- 👤 John E. McGowan
- 👤 William C. Plants
- 👤 Joel D. Landry
- 👤 Sinan Kaptanoglu
- 👤 Warren K. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/17704
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
349 words
A field programmable gate array architecture comprising: a plurality of horizontal routing channels each including a plurality of interconnect conductors, some of said interconnect conductors segmented by user-programmable interconnect elements; a plurality of vertical routing channels each including a plurality of interconnect conductors forming intersections with interconnect conductors in said horizontal routing channels, some of said interconnect conductors segmented by user-programmable interconnect elements; user-programmable interconnect elements connected between selected ones of said horizontal and vertical interconnect conductors at selected ones of said intersections; an array comprising a plurality of rows and columns of logic function modules superimposed on said horizontal and vertical routing channels, each of said logic function modules having at least one input and at least one output, said at least one input and at least one output of said logic function modules connectable to ones of said interconnect conductors in either or both of said horizontal and vertical routing channels; at least a portion of one column of said array including random access memory blocks disposed in said array in place of logic function modules, said at least a portion of a column adjacent to at least one column of said logic function modules, each of said random access memory blocks spanning a distance of more than one row of said array such that at least one interconnect conductor in more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof; each of said random access memory blocks having address inputs, control inputs, data inputs, and data outputs; user-programmable interconnect elements connected between said address inputs, control inputs, data inputs, and data outputs of said random access memory blocks and selected ones of said interconnect conductors in said more than one horizontal routing channel passing therethrough; and means for programming selected ones of said user-programmable interconnect conductors to connect the at least one input and at least one output of ones of said logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of said random access memory blocks.
Claim 2
Dependent Claim
349 words
A field programmable gate array architecture comprising: a plurality of horizontal routing channels each including a plurality of interconnect conductors, some of said interconnect conductors segmented by user-programmable interconnect elements; a plurality of vertical routing channels each including a plurality of interconnect conductors forming intersections with interconnect conductors in said horizontal routing channels, some of said interconnect conductors segmented by user-programmable interconnect elements; user-programmable interconnect elements connected between selected ones of said horizontal and vertical interconnect conductors at selected ones of said intersections; an array comprising a plurality of rows and columns of logic function modules superimposed on said horizontal and vertical routing channels, each of said logic function modules having at least one input and at least one output, said at least one input and at least one output of said logic function modules connectable to ones of said interconnect conductors in either or both of said horizontal and vertical routing channels; at least a portion of one column of said array including random access memory blocks disposed in said array in place of logic function modules, said at least a portion of a column adjacent to at least one column of said logic function modules, each of said random access memory blocks spanning a distance of more than one row of said array such that at least one interconnect conductor in more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof; each of said random access memory blocks having address inputs, control inputs, data inputs, and data outputs; user-programmable interconnect elements connected between said address inputs, control inputs, data inputs, and data outputs of said random access memory blocks and selected ones of said interconnect conductors in said more than one horizontal routing channel passing therethrough; and means for programming selected ones of said user-programmable interconnect conductors to connect the at least one input and at least one output of ones of said logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of said random access memory blocks.
Claim 3
Dependent Claim
23 words
The field programmable gate array architecture of claim 1 wherein said random access memory blocks are dual ported static random access memory blocks.
Claim 4
Dependent Claim
40 words
The field programmable gate array architecture of claim 1 wherein one of said control inputs of said random access memory blocks is a mode control input for selecting between a first data bus width and a second data bus width.
Claim 5
Dependent Claim
27 words
The field programmable gate array architecture of claim 3 wherein said first data bus width is eight bits and said second data bus width is four bits.
Claim 6
Dependent Claim
75 words
The field programmable gate array architecture of claim 1 wherein one of said control inputs of said random access memory blocks is a write clock input polarity control input having two states, a first state in which write operations are initiated on a rising edge of a write clock input to said random access memory blocks and a second state in which write operations are initiated on a falling edge of said write clock input.
Claim 7
Dependent Claim
102 words
The field programmable gate array architecture of claim 1 wherein said random access memory blocks include a block enable input for enabling said random access memory blocks and wherein one of said control inputs of said random access memory blocks is a block enable input polarity control input having two states, a first state in which said random access memory blocks are enabled by a logic high signal on said block enable input to said random access memory blocks and a second state in which said random access memory blocks are enabled by a logic low signal on said block enable input.
Claim 8
Dependent Claim
77 words
The field programmable gate array architecture of claim 1 wherein said random access memory blocks include read address latches and read data output latches, each of said read address latches and read data output latches having a transparent state and a latched state, the transparent states and the latched states of the read address latches and read data output latches being responsive to opposite logic states of a read clock input to said random access memory blocks.
Claim 9
Dependent Claim
353 words
A field programmable gate array architecture comprising: a plurality of horizontal routing channels each including a plurality of interconnect conductors, some of said interconnect conductors segmented by user-programmable interconnect elements; a plurality of vertical routing channels each including a plurality of interconnect conductors forming intersections with interconnect conductors in said horizontal routing channels, some of said interconnect conductors segmented by user-programmable interconnect elements; user-programmable interconnect elements connected between selected ones of said horizontal and vertical interconnect conductors at selected ones of said intersections; an array comprising a plurality of rows and columns of logic function modules superimposed on said horizontal and vertical routing channels, each of said logic function modules having at least one input and at least one output, said at least one input and at least one output of said logic function modules connectable to ones of said interconnect conductors in either or both of said horizontal and vertical routing channels; at least a portion of more than one column of said array including random access memory blocks disposed in said array in place of logic function modules, said at least a portion of more than one column adjacent to at least one column of said logic function modules, each of said random access memory blocks spanning a distance of more than one row of said array such that at least one interconnect conductor in more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof; each of said random access memory blocks having address inputs, control inputs, data inputs, and data outputs; user-programmable interconnect elements connected between said address inputs, control inputs, data inputs, and data outputs of said random access memory blocks and selected ones of said interconnect conductors in said more than one horizontal routing channel passing therethrough; and means for programming selected ones of said user-programmable interconnect conductors to connect the at least one input and at least one output of ones of said logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of said random access memory blocks.
Claim 10
Dependent Claim
353 words
A field programmable gate array architecture comprising: a plurality of horizontal routing channels each including a plurality of interconnect conductors, some of said interconnect conductors segmented by user-programmable interconnect elements; a plurality of vertical routing channels each including a plurality of interconnect conductors forming intersections with interconnect conductors in said horizontal routing channels, some of said interconnect conductors segmented by user-programmable interconnect elements; user-programmable interconnect elements connected between selected ones of said horizontal and vertical interconnect conductors at selected ones of said intersections; an array comprising a plurality of rows and columns of logic function modules superimposed on said horizontal and vertical routing channels, each of said logic function modules having at least one input and at least one output, said at least one input and at least one output of said logic function modules connectable to ones of said interconnect conductors in either or both of said horizontal and vertical routing channels; at least a portion of more than one column of said array including random access memory blocks disposed in said array in place of logic function modules, said at least a portion of more than one column adjacent to at least one column of said logic function modules, each of said random access memory blocks spanning a distance of more than one row of said array such that at least one interconnect conductor in more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof; each of said random access memory blocks having address inputs, control inputs, data inputs, and data outputs; user-programmable interconnect elements connected between said address inputs, control inputs, data inputs, and data outputs of said random access memory blocks and selected ones of said interconnect conductors in said more than one horizontal routing channel passing therethrough; and means for programming selected ones of said user-programmable interconnect conductors to connect the at least one input and at least one output of ones of said logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of said random access memory blocks.
Claim 11
Dependent Claim
23 words
The field programmable gate array architecture of claim 8 wherein said random access memory blocks are dual ported static random access memory blocks.
Claim 12
Dependent Claim
40 words
The field programmable gate array architecture of claim 8 wherein one of said control inputs of said random access memory blocks is a mode control input for selecting between a first data bus width and a second data bus width.
Claim 13
Dependent Claim
27 words
The field programmable gate array architecture of claim 10 wherein said first data bus width is eight bits and said second data bus width is four bits.
Claim 14
Dependent Claim
75 words
The field programmable gate array architecture of claim 8 wherein one of said control inputs of said random access memory blocks is a write clock input polarity control input having two states, a first state in which write operations are initiated on a rising edge of a write clock input to said random access memory blocks and a second state in which write operations are initiated on a falling edge of said write clock input.
Claim 15
Dependent Claim
102 words
The field programmable gate array architecture of claim 8 wherein said random access memory blocks include a block enable input for enabling said random access memory blocks and wherein one of said control inputs of said random access memory blocks is a block enable input polarity control input having two states, a first state in which said random access memory blocks are enabled by a logic high signal on said block enable input to said random access memory blocks and a second state in which said random access memory blocks are enabled by a logic low signal on said block enable input.
Claim 16
Dependent Claim
77 words
The field programmable gate array architecture of claim 8 wherein said random access memory blocks include read address latches and read data output latches, each of said read address latches and read data output latches having a transparent state and a latched state, the transparent states and the latched states of the read address latches and read data output latches being responsive to opposite logic states of a read clock input to said random access memory blocks.
References Cited (Backward Citations)
US3818452A
Cited
US3816725A
Cited
US3849638A
Cited
US3987287A
Cited
US4293783A
Cited
US4433331A
Cited
US4717912A
Cited
US4847732A
Cited
EP0162529A1
Cited
US4870302A
Cited
US4701922A
Cited
US4713557A
Cited
US4642487A
Cited
US4758985A
Cited
US4963768A
Cited
US4742252A
Cited
US5151623A
Cited
US4677318A
Cited
US4706208A
Cited
US4763020A
Cited
US4763020B1
Cited
WO1987002827A1
Cited
US4821176A
Cited
US4823181A
Cited
US4789951A
Cited
US4870300A
Cited
US5172014A
Cited
US5015885A
Cited
US4873459A
Cited
US5187393A
Cited
US4758745B1
Cited
US4910417A
Cited
US4857774A
Cited
US5083083A
Cited
US4873459B1
Cited
US4758745A
Cited
US5019736A
Cited
US4786904A
Cited
US4963770A
Cited
EP0394575A1
Cited
US5023606A
Cited
US4847612A
Cited
US4903223A
Cited
US4871930A
Cited
DE3927033A1
Cited
US5003200A
Cited
US5001368A
Cited
EP0410759A2
Cited
US5233539A
Cited
US4914055A
Cited
US5400262A
Cited
US5140193A
Cited
EP0452091A2
Cited
US5070384A
Cited
US5181096A
Cited
US5055718A
Cited
US5073729A
Cited
US5132571A
Cited
US5245227A
Cited
US5144166A
Cited
US5220213A
Cited
US5122685A
Cited
US5313119A
Cited
EP0507507A2
Cited
US5260611A
Cited
US5559971A
Cited
US5171715A
Cited
US5258668A
Cited
US5331226A
Cited
US5291079A
Cited
US5302866A
Cited
US5548228A
Cited
US5570040A
Cited
US5559450A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-27 | 2001-10-27 | 2002-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-27 | 2005-10-27 | 2006-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-27 | 2009-10-27 | 2010-04-28 | $7700.00 | Window Closed / Lapsed |